Qualcomm Technologies EMAC Gigabit Ethernet Controller
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This network controller consists of two devices: a MAC and an SGMII
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internal PHY. Each device is represented by a device tree node. A phandle
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connects the MAC node to its corresponding internal phy node. Another
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phandle points to the external PHY node.
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Required properties:
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MAC node:
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- compatible : Should be "qcom,fsm9900-emac".
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- reg : Offset and length of the register regions for the device
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- interrupts : Interrupt number used by this controller
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- mac-address : The 6-byte MAC address. If present, it is the default
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MAC address.
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- internal-phy : phandle to the internal PHY node
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- phy-handle : phandle the the external PHY node
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Internal PHY node:
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- compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
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- reg : Offset and length of the register region(s) for the device
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- interrupts : Interrupt number used by this controller
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The external phy child node:
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- reg : The phy address
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Example:
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FSM9900:
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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emac0: ethernet@feb20000 {
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compatible = "qcom,fsm9900-emac";
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reg = <0xfeb20000 0x10000>,
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<0xfeb36000 0x1000>;
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interrupts = <76>;
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clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
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<&gcc 6>, <&gcc 7>;
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clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
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"mdio_clk", "tx_clk", "rx_clk", "sys_clk";
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internal-phy = <&emac_sgmii>;
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phy-handle = <&phy0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins_a>;
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};
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emac_sgmii: ethernet@feb38000 {
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compatible = "qcom,fsm9900-emac-sgmii";
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reg = <0xfeb38000 0x1000>;
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interrupts = <80>;
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};
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tlmm: pinctrl@fd510000 {
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compatible = "qcom,fsm9900-pinctrl";
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mdio_pins_a: mdio {
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state {
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pins = "gpio123", "gpio124";
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function = "mdio";
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};
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};
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};
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QDF2432:
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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emac0: ethernet@38800000 {
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compatible = "qcom,fsm9900-emac";
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reg = <0x0 0x38800000 0x0 0x10000>,
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<0x0 0x38816000 0x0 0x1000>;
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interrupts = <0 256 4>;
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clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
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<&gcc 6>, <&gcc 7>;
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clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
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"mdio_clk", "tx_clk", "rx_clk", "sys_clk";
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internal-phy = <&emac_sgmii>;
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phy-handle = <&phy0>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@4 {
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reg = <4>;
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};
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};
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emac_sgmii: ethernet@410400 {
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compatible = "qcom,qdf2432-emac-sgmii";
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reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */
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<0x0 0x00410000 0x0 0x400>; /* Per-lane digital */
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interrupts = <0 254 1>;
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};
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