/*
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* Copyright (c) 2013 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <dwmmc.h>
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#include <errno.h>
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#include <mapmem.h>
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#include <pwrseq.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/periph.h>
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#include <linux/err.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rockchip_mmc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3288_dw_mshc dtplat;
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#endif
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct rockchip_dwmmc_priv {
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struct clk clk;
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struct clk sample_clk;
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struct dwmci_host host;
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int fifo_depth;
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bool fifo_mode;
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u32 minmax[2];
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};
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#ifdef CONFIG_USING_KERNEL_DTB
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int board_mmc_dm_reinit(struct udevice *dev)
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{
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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if (!priv)
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return 0;
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if (!memcmp(dev->name, "dwmmc", strlen("dwmmc")))
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return clk_get_by_index(dev, 0, &priv->clk);
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else
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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__weak void mmc_gpio_init_direct(void) {}
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#endif
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static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
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{
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struct udevice *dev = host->priv;
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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int ret;
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/*
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* If DDR52 8bit mode(only emmc work in 8bit mode),
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* divider must be set 1
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*/
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if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8)
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freq *= 2;
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ret = clk_set_rate(&priv->clk, freq);
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if (ret < 0) {
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debug("%s: err=%d\n", __func__, ret);
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return 0;
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}
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return freq;
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}
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static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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host->name = dev->name;
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host->ioaddr = dev_read_addr_ptr(dev);
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host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
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host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
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host->priv = dev;
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/* use non-removeable as sdcard and emmc as judgement */
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if (dev_read_bool(dev, "non-removable"))
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host->dev_index = 0;
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else
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host->dev_index = 1;
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priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
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if (priv->fifo_depth < 0)
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return -EINVAL;
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priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
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/*
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* 'clock-freq-min-max' is deprecated
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* (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
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*/
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if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
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int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
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if (val < 0)
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return val;
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priv->minmax[0] = 400000; /* 400 kHz */
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priv->minmax[1] = val;
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} else {
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debug("%s: 'clock-freq-min-max' property was deprecated.\n",
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__func__);
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}
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#endif
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return 0;
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}
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#ifndef CONFIG_MMC_SIMPLE
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static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode)
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{
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int i = 0;
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int ret = -1;
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struct mmc *mmc = host->mmc;
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struct udevice *dev = host->priv;
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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if (IS_ERR(&priv->sample_clk))
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return -EIO;
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if (mmc->default_phase > 0 && mmc->default_phase < 360) {
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ret = clk_set_phase(&priv->sample_clk, mmc->default_phase);
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if (ret)
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printf("set clk phase fail\n");
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else
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ret = mmc_send_tuning(mmc, opcode);
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mmc->default_phase = 0;
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}
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/*
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* If use default_phase to tune successfully, return.
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* Otherwise, use the othe phase to tune.
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*/
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if (!ret)
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return ret;
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for (i = 0; i < 5; i++) {
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/* mmc->init_retry must be 0, 1, 2, 3 */
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if (mmc->init_retry == 4)
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mmc->init_retry = 0;
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ret = clk_set_phase(&priv->sample_clk, 90 * mmc->init_retry);
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if (ret) {
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printf("set clk phase fail\n");
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break;
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}
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ret = mmc_send_tuning(mmc, opcode);
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debug("Tuning phase is %d, ret is %d\n", mmc->init_retry * 90, ret);
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mmc->init_retry++;
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if (!ret)
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break;
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}
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return ret;
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}
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#else
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static int rockchip_dwmmc_execute_tuning(struct dwmci_host *host, u32 opcode) { return 0; }
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#endif
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static int rockchip_dwmmc_probe(struct udevice *dev)
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{
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struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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struct udevice *pwr_dev __maybe_unused;
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int ret;
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#ifdef CONFIG_SPL_BUILD
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mmc_gpio_init_direct();
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#endif
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
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host->name = dev->name;
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host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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host->buswidth = dtplat->bus_width;
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host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
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host->execute_tuning = rockchip_dwmmc_execute_tuning;
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host->priv = dev;
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host->dev_index = 0;
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priv->fifo_depth = dtplat->fifo_depth;
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priv->fifo_mode = 0;
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priv->minmax[0] = 400000; /* 400 kHz */
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priv->minmax[1] = dtplat->max_frequency;
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ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
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if (ret < 0)
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return ret;
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#else
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_get_by_name(dev, "ciu-sample", &priv->sample_clk);
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if (ret < 0)
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debug("MMC: sample clock not found, not support hs200!\n");
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host->execute_tuning = rockchip_dwmmc_execute_tuning;
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#endif
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host->fifoth_val = MSIZE(DWMCI_MSIZE) |
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RX_WMARK(priv->fifo_depth / 2 - 1) |
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TX_WMARK(priv->fifo_depth / 2);
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host->fifo_mode = priv->fifo_mode;
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#ifdef CONFIG_ROCKCHIP_RK3128
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host->stride_pio = true;
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#else
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host->stride_pio = false;
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#endif
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#ifdef CONFIG_PWRSEQ
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/* Enable power if needed */
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ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
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&pwr_dev);
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if (!ret) {
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ret = pwrseq_set_power(pwr_dev, true);
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if (ret)
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return ret;
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}
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#endif
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dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
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if (dev_read_bool(dev, "mmc-hs200-1_8v"))
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plat->cfg.host_caps |= MMC_MODE_HS200;
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plat->mmc.default_phase =
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dev_read_u32_default(dev, "default-sample-phase", 0);
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#ifdef CONFIG_ROCKCHIP_RV1106
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if (!(ret < 0) && (&priv->sample_clk)) {
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ret = clk_set_phase(&priv->sample_clk, plat->mmc.default_phase);
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if (ret < 0)
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debug("MMC: can not set default phase!\n");
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}
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#endif
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plat->mmc.init_retry = 0;
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host->mmc = &plat->mmc;
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host->mmc->priv = &priv->host;
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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return dwmci_probe(dev);
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}
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static int rockchip_dwmmc_bind(struct udevice *dev)
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{
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struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
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return dwmci_bind(dev, &plat->mmc, &plat->cfg);
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}
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static const struct udevice_id rockchip_dwmmc_ids[] = {
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{ .compatible = "rockchip,rk3288-dw-mshc" },
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{ .compatible = "rockchip,rk2928-dw-mshc" },
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{ }
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};
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U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
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.name = "rockchip_rk3288_dw_mshc",
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.id = UCLASS_MMC,
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.of_match = rockchip_dwmmc_ids,
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.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
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.ops = &dm_dwmci_ops,
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.bind = rockchip_dwmmc_bind,
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.probe = rockchip_dwmmc_probe,
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.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
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.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
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};
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#ifdef CONFIG_PWRSEQ
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static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
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{
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struct gpio_desc reset;
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int ret;
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ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
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if (ret)
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return ret;
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dm_gpio_set_value(&reset, 1);
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udelay(1);
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dm_gpio_set_value(&reset, 0);
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udelay(200);
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return 0;
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}
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static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
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.set_power = rockchip_dwmmc_pwrseq_set_power,
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};
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static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
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{ .compatible = "mmc-pwrseq-emmc" },
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{ }
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};
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U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
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.name = "mmc_pwrseq_emmc",
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.id = UCLASS_PWRSEQ,
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.of_match = rockchip_dwmmc_pwrseq_ids,
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.ops = &rockchip_dwmmc_pwrseq_ops,
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};
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#endif
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