/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd
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*/
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#ifndef __SOC_ROCKCHIP_PERFORMANCE_H
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#define __SOC_ROCKCHIP_PERFORMANCE_H
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enum {
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ROCKCHIP_PERFORMANCE_LOW = 0,
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ROCKCHIP_PERFORMANCE_NORMAL,
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ROCKCHIP_PERFORMANCE_HIGH
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};
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#ifdef CONFIG_ROCKCHIP_PERFORMANCE
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extern int rockchip_perf_get_level(void);
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extern struct cpumask *rockchip_perf_get_cpul_mask(void);
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extern struct cpumask *rockchip_perf_get_cpub_mask(void);
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extern int rockchip_perf_select_rt_cpu(int prev_cpu, struct cpumask *lowest_mask);
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extern bool rockchip_perf_misfit_rt(int cpu);
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extern void rockchip_perf_uclamp_sync_util_min_rt_default(void);
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#else
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static inline int rockchip_perf_get_level(void) { return ROCKCHIP_PERFORMANCE_NORMAL; }
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static inline struct cpumask *rockchip_perf_get_cpul_mask(void) { return NULL; };
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static inline struct cpumask *rockchip_perf_get_cpub_mask(void) { return NULL; };
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static inline int rockchip_perf_select_rt_cpu(int prev_cpu, struct cpumask *lowest_mask)
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{
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return prev_cpu;
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}
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static inline bool rockchip_perf_misfit_rt(int cpu) { return false; }
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static inline void rockchip_perf_uclamp_sync_util_min_rt_default(void) {}
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#endif
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#endif
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