// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Rockchip Electronics Co., Ltd.
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*
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* Author: Huang Lee <Putin.li@rock-chips.com>
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*/
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#define pr_fmt(fmt) "rve_reg: " fmt
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#include "rve_reg.h"
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#include "rve_job.h"
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void rve_soft_reset(struct rve_scheduler_t *scheduler)
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{
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u32 i;
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u32 reg;
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rve_write(1, RVE_SWREG5_IVE_IDLE_CTRL, scheduler);
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if (DEBUGGER_EN(REG)) {
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pr_err("dump reg info on soft reset");
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rve_dump_read_back_reg(scheduler);
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}
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if (DEBUGGER_EN(MSG)) {
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pr_err("soft reset idle_ctrl = %.8x, idle_prc_sta = %.8x",
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rve_read(RVE_SWREG5_IVE_IDLE_CTRL, scheduler),
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rve_read(RVE_SWREG3_IVE_IDLE_PRC_STA, scheduler));
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pr_err("work status = %.8x", rve_read(RVE_SWREG6_IVE_WORK_STA, scheduler));
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}
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mdelay(20);
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for (i = 0; i < RVE_RESET_TIMEOUT; i++) {
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reg = rve_read(RVE_SWREG3_IVE_IDLE_PRC_STA, scheduler);
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if (reg & 0x2) {
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pr_info("soft reset successfully");
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/* reset sw_softrst_rdy_sta reg */
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rve_write(0x30000, RVE_SWREG3_IVE_IDLE_PRC_STA, scheduler);
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/* reset RVE_SWREG6_IVE_WORK_STA */
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rve_write(0xff0000, RVE_SWREG6_IVE_WORK_STA, scheduler);
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/* clean up int */
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rve_write(0x30000, RVE_SWREG1_IVE_IRQ, scheduler);
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break;
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}
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udelay(1);
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}
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if (i == RVE_RESET_TIMEOUT)
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pr_err("soft reset timeout.\n");
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if (DEBUGGER_EN(MSG)) {
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pr_err("after soft reset idle_ctrl = %.8x, idle_prc_sta = %.8x",
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rve_read(RVE_SWREG5_IVE_IDLE_CTRL, scheduler),
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rve_read(RVE_SWREG3_IVE_IDLE_PRC_STA, scheduler));
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pr_err("work status = %x", rve_read(RVE_SWREG6_IVE_WORK_STA, scheduler));
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}
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}
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int rve_init_reg(struct rve_job *job)
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{
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int ret = 0;
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if (DEBUGGER_EN(MSG))
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pr_err("TODO: debug info");
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return ret;
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}
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void rve_dump_read_back_reg(struct rve_scheduler_t *scheduler)
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{
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int i;
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unsigned long flags;
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uint32_t sys_reg[8] = {0};
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uint32_t ltb_reg[12] = {0};
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uint32_t cfg_reg[40] = {0};
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uint32_t mmu_reg[12] = {0};
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spin_lock_irqsave(&scheduler->irq_lock, flags);
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for (i = 0; i < 8; i++)
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sys_reg[i] = rve_read(RVE_SYS_REG + i * 4, scheduler);
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for (i = 0; i < 12; i++)
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ltb_reg[i] = rve_read(RVE_LTB_REG + i * 4, scheduler);
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for (i = 0; i < 40; i++)
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cfg_reg[i] = rve_read(RVE_CFG_REG + i * 4, scheduler);
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for (i = 0; i < 12; i++)
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mmu_reg[i] = rve_read(RVE_MMU_REG + i * 4, scheduler);
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spin_unlock_irqrestore(&scheduler->irq_lock, flags);
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pr_info("sys_reg:");
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for (i = 0; i < 2; i++)
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pr_info("i = %x : %.8x %.8x %.8x %.8x\n", RVE_SYS_REG + i * 16,
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sys_reg[0 + i * 4], sys_reg[1 + i * 4],
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sys_reg[2 + i * 4], sys_reg[3 + i * 4]);
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pr_info("ltb_reg:");
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for (i = 0; i < 3; i++)
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pr_info("i = %x : %.8x %.8x %.8x %.8x\n", RVE_LTB_REG + i * 16,
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ltb_reg[0 + i * 4], ltb_reg[1 + i * 4],
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ltb_reg[2 + i * 4], ltb_reg[3 + i * 4]);
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pr_info("cfg_reg:");
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for (i = 0; i < 10; i++)
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pr_info("i = %x : %.8x %.8x %.8x %.8x\n", RVE_CFG_REG + i * 16,
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cfg_reg[0 + i * 4], cfg_reg[1 + i * 4],
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cfg_reg[2 + i * 4], cfg_reg[3 + i * 4]);
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pr_info("mmu_reg:");
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for (i = 0; i < 3; i++)
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pr_info("i = %x : %.8x %.8x %.8x %.8x\n", RVE_MMU_REG + i * 16,
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mmu_reg[0 + i * 4], mmu_reg[1 + i * 4],
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mmu_reg[2 + i * 4], mmu_reg[3 + i * 4]);
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}
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int rve_set_reg(struct rve_job *job, struct rve_scheduler_t *scheduler)
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{
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ktime_t now = ktime_get();
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//uint32_t cmd_reg[58];
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uint32_t *cmd_reg;
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int i;
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cmd_reg = job->regcmd_data->cmd_reg;
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if (DEBUGGER_EN(REG)) {
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pr_info("user readback:");
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for (i = 0; i < 14; i++)
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pr_info("%.8x %.8x %.8x %.8x\n",
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cmd_reg[0 + i * 4], cmd_reg[1 + i * 4],
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cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
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pr_info("%.8x %.8x", cmd_reg[56], cmd_reg[57]);
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}
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/* clean up irq status reg */
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rve_write(0x00000, RVE_SWREG6_IVE_WORK_STA, scheduler);
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if (DEBUGGER_EN(MSG)) {
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pr_info("idle_ctrl = %x, idle_prc_sta = %x",
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rve_read(RVE_SWREG5_IVE_IDLE_CTRL, scheduler),
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rve_read(RVE_SWREG3_IVE_IDLE_PRC_STA, scheduler));
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pr_info("work status = %x", rve_read(RVE_SWREG6_IVE_WORK_STA, scheduler));
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}
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if (DEBUGGER_EN(TIME))
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pr_info("set cmd use time = %lld\n", ktime_to_us(ktime_sub(now, job->timestamp)));
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job->hw_running_time = now;
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job->hw_recoder_time = now;
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/* start hw, CMD buff */
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for (i = 0; i < 8; i++)
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rve_write(cmd_reg[i], RVE_SYS_REG + i * 4, scheduler);
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for (i = 0; i < 10; i++) {
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/* skip start reg */
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if (i == 2)
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continue;
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rve_write(cmd_reg[8 + i], RVE_LTB_REG + i * 4, scheduler);
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}
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/* 0x200(start)(40 - 1 = 39) need config after reg ready */
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for (i = 0; i < 39; i++)
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rve_write(cmd_reg[19 + i], RVE_CFG_REG + (i + 1) * 4, scheduler);
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//TODO: ddr config
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rve_write(0x30000, RVE_SWCFG5_CTRL, scheduler);
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rve_write(0xf4240, RVE_SWCFG6_TIMEOUT_THRESH, scheduler);
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rve_write(0x1f0001, RVE_SWCFG7_DDR_CTRL, scheduler);
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/* reset RVE_SWREG6_IVE_WORK_STA */
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rve_write(RVE_CLEAR_UP_REG6_WROK_STA, RVE_SWREG6_IVE_WORK_STA, scheduler);
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/* enable monitor */
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if (DEBUGGER_EN(MONITOR))
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rve_write(1, RVE_SWCFG32_MONITOR_CTRL0, scheduler);
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if (DEBUGGER_EN(REG)) {
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pr_err("before config:");
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rve_dump_read_back_reg(scheduler);
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}
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/* if llp mode enable, skip to enable slave mode */
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if (cmd_reg[11] != 1)
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rve_write(1, RVE_SWCFG0_EN, scheduler);
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else
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/* llp config done, to start hw */
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rve_write(cmd_reg[10], RVE_SWLTB2_CFG_DONE, scheduler);
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if (DEBUGGER_EN(REG)) {
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pr_err("after config:");
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rve_dump_read_back_reg(scheduler);
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}
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return 0;
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}
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int rve_get_version(struct rve_scheduler_t *scheduler)
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{
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u32 major_version, minor_version, prod_num;
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u32 reg_version;
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if (!scheduler) {
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pr_err("scheduler is null\n");
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return -EINVAL;
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}
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reg_version = rve_read(RVE_SWREG0_IVE_VERSION, scheduler);
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major_version = (reg_version & RVE_MAJOR_VERSION_MASK) >> 8;
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minor_version = (reg_version & RVE_MINOR_VERSION_MASK);
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prod_num = (reg_version & RVE_PROD_NUM_MASK) >> 16;
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snprintf(scheduler->version.str, sizeof(scheduler->version.str), "[%x]%x.%x",
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prod_num, major_version, minor_version);
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scheduler->version.major = major_version;
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scheduler->version.minor = minor_version;
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scheduler->version.prod_num = prod_num;
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return 0;
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}
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void rve_get_monitor_info(struct rve_job *job)
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{
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struct rve_sche_pid_info_t *pid_info = NULL;
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struct rve_scheduler_t *scheduler = NULL;
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unsigned long flags;
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uint32_t rd_bandwidth, wr_bandwidth, cycle_cnt;
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int i;
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scheduler = rve_job_get_scheduler(job);
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pid_info = scheduler->session.pid_info;
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/* monitor */
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if (DEBUGGER_EN(MONITOR)) {
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rd_bandwidth = rve_read(RVE_SWCFG37_MONITOR_INFO3, scheduler);
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wr_bandwidth = rve_read(RVE_SWCFG38_MONITOR_INFO4, scheduler);
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cycle_cnt = rve_read(RVE_SWCFG39_MONITOR_INFO5, scheduler);
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/* reset per htimer occur */
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rve_write(2, RVE_SWCFG32_MONITOR_CTRL0, scheduler);
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spin_lock_irqsave(&scheduler->irq_lock, flags);
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for (i = 0; i < RVE_MAX_PID_INFO; i++) {
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if (pid_info[i].pid == job->pid) {
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pid_info[i].last_job_rd_bandwidth = rd_bandwidth;
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pid_info[i].last_job_wr_bandwidth = wr_bandwidth;
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pid_info[i].last_job_cycle_cnt = cycle_cnt;
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break;
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}
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}
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if (DEBUGGER_EN(MSG))
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pr_info("rd_bandwidth = %d, wd_bandwidth = %d, cycle_cnt = %d\n",
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rd_bandwidth, wr_bandwidth, cycle_cnt);
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scheduler->session.rd_bandwidth += rd_bandwidth;
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scheduler->session.wr_bandwidth += wr_bandwidth;
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scheduler->session.cycle_cnt += cycle_cnt;
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spin_unlock_irqrestore(&scheduler->irq_lock, flags);
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}
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}
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