/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _RGA_DRIVER_H_
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#define _RGA_DRIVER_H_
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#include <linux/mutex.h>
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#include <linux/scatterlist.h>
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/* Use 'r' as magic number */
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#define RGA_IOC_MAGIC 'r'
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#define RGA_IOW(nr, type) _IOW(RGA_IOC_MAGIC, nr, type)
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#define RGA_IOR(nr, type) _IOR(RGA_IOC_MAGIC, nr, type)
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#define RGA_IOWR(nr, type) _IOWR(RGA_IOC_MAGIC, nr, type)
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#define RGA_IOC_GET_DRVIER_VERSION RGA_IOR(0x1, struct rga_version_t)
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#define RGA_IOC_GET_HW_VERSION RGA_IOR(0x2, struct rga_hw_versions_t)
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#define RGA_IOC_IMPORT_BUFFER RGA_IOWR(0x3, struct rga_buffer_pool)
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#define RGA_IOC_RELEASE_BUFFER RGA_IOW(0x4, struct rga_buffer_pool)
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#define RGA_IOC_REQUEST_CREATE RGA_IOR(0x5, uint32_t)
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#define RGA_IOC_REQUEST_SUBMIT RGA_IOWR(0x6, struct rga_user_request)
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#define RGA_IOC_REQUEST_CONFIG RGA_IOWR(0x7, struct rga_user_request)
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#define RGA_IOC_REQUEST_CANCEL RGA_IOWR(0x8, uint32_t)
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#define RGA_BLIT_SYNC 0x5017
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#define RGA_BLIT_ASYNC 0x5018
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#define RGA_FLUSH 0x5019
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#define RGA_GET_RESULT 0x501a
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#define RGA_GET_VERSION 0x501b
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#define RGA_CACHE_FLUSH 0x501c
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#define RGA2_GET_VERSION 0x601b
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#define RGA_IMPORT_DMA 0x601d
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#define RGA_RELEASE_DMA 0x601e
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#define RGA_TASK_NUM_MAX 50
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#define RGA_OUT_OF_RESOURCES -10
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#define RGA_MALLOC_ERROR -11
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#define SCALE_DOWN_LARGE 1
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#define SCALE_UP_LARGE 1
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#define RGA_BUFFER_POOL_SIZE_MAX 40
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#define RGA3_MAJOR_VERSION_MASK (0xF0000000)
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#define RGA3_MINOR_VERSION_MASK (0x0FF00000)
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#define RGA3_SVN_VERSION_MASK (0x000FFFFF)
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#define RGA2_MAJOR_VERSION_MASK (0xFF000000)
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#define RGA2_MINOR_VERSION_MASK (0x00F00000)
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#define RGA2_SVN_VERSION_MASK (0x000FFFFF)
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#define RGA_MODE_ROTATE_0 (1<<0)
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#define RGA_MODE_ROTATE_90 (1<<1)
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#define RGA_MODE_ROTATE_180 (1<<2)
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#define RGA_MODE_ROTATE_270 (1<<3)
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#define RGA_MODE_X_MIRROR (1<<4)
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#define RGA_MODE_Y_MIRROR (1<<5)
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#define RGA_MODE_CSC_BT601L (1<<0)
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#define RGA_MODE_CSC_BT601F (1<<1)
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#define RGA_MODE_CSC_BT709 (1<<2)
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#define RGA_MODE_CSC_BT2020 (1<<3)
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#define RGA_MODE_ROTATE_MASK (\
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RGA_MODE_ROTATE_0 | \
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RGA_MODE_ROTATE_90 | \
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RGA_MODE_ROTATE_180 | \
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RGA_MODE_ROTATE_270 | \
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RGA_MODE_X_MIRROR | \
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RGA_MODE_Y_MIRROR)
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enum rga_memory_type {
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RGA_DMA_BUFFER = 0,
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RGA_VIRTUAL_ADDRESS,
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RGA_PHYSICAL_ADDRESS,
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RGA_DMA_BUFFER_PTR,
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};
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enum rga_scale_up_mode {
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RGA_SCALE_UP_NONE = 0x0,
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RGA_SCALE_UP_BIC = 0x1,
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};
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enum rga_scale_down_mode {
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RGA_SCALE_DOWN_NONE = 0x0,
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RGA_SCALE_DOWN_AVG = 0x1,
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};
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/* RGA process mode enum */
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enum {
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BITBLT_MODE = 0x0,
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COLOR_PALETTE_MODE = 0x1,
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COLOR_FILL_MODE = 0x2,
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/* used by rga2 */
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UPDATE_PALETTE_TABLE_MODE = 0x6,
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UPDATE_PATTEN_BUF_MODE = 0x7,
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}; /*render mode*/
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/* RGA rd_mode */
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enum {
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RGA_RASTER_MODE = 0x1 << 0,
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RGA_FBC_MODE = 0x1 << 1,
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RGA_TILE_MODE = 0x1 << 2,
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};
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enum {
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RGA_10BIT_COMPACT = 0x0,
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RGA_10BIT_INCOMPACT = 0x1,
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};
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enum {
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RGA_CONTEXT_NONE = 0x0,
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RGA_CONTEXT_SRC_FIX_ENABLE = 0x1 << 0,
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RGA_CONTEXT_SRC_CACHE_INFO = 0x1 << 1,
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RGA_CONTEXT_SRC_MASK = RGA_CONTEXT_SRC_FIX_ENABLE |
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RGA_CONTEXT_SRC_CACHE_INFO,
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RGA_CONTEXT_PAT_FIX_ENABLE = 0x1 << 2,
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RGA_CONTEXT_PAT_CACHE_INFO = 0x1 << 3,
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RGA_CONTEXT_PAT_MASK = RGA_CONTEXT_PAT_FIX_ENABLE |
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RGA_CONTEXT_PAT_CACHE_INFO,
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RGA_CONTEXT_DST_FIX_ENABLE = 0x1 << 4,
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RGA_CONTEXT_DST_CACHE_INFO = 0x1 << 5,
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RGA_CONTEXT_DST_MASK = RGA_CONTEXT_DST_FIX_ENABLE |
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RGA_CONTEXT_DST_CACHE_INFO,
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};
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/* RGA feature */
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enum {
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RGA_COLOR_FILL = 0x1 << 0,
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RGA_COLOR_PALETTE = 0x1 << 1,
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RGA_COLOR_KEY = 0x1 << 2,
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RGA_ROP_CALCULATE = 0x1 << 3,
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RGA_NN_QUANTIZE = 0x1 << 4,
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RGA_OSD_BLEND = 0x1 << 5,
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RGA_DITHER = 0x1 << 6,
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RGA_MOSAIC = 0x1 << 7,
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RGA_YIN_YOUT = 0x1 << 8,
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RGA_YUV_HDS = 0x1 << 9,
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RGA_YUV_VDS = 0x1 << 10,
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RGA_OSD = 0x1 << 11,
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RGA_PRE_INTR = 0x1 << 12,
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RGA_FULL_CSC = 0x1 << 13,
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};
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enum rga_surf_format {
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RGA_FORMAT_RGBA_8888 = 0x0,
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RGA_FORMAT_RGBX_8888 = 0x1,
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RGA_FORMAT_RGB_888 = 0x2,
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RGA_FORMAT_BGRA_8888 = 0x3,
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RGA_FORMAT_RGB_565 = 0x4,
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RGA_FORMAT_RGBA_5551 = 0x5,
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RGA_FORMAT_RGBA_4444 = 0x6,
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RGA_FORMAT_BGR_888 = 0x7,
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RGA_FORMAT_YCbCr_422_SP = 0x8,
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RGA_FORMAT_YCbCr_422_P = 0x9,
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RGA_FORMAT_YCbCr_420_SP = 0xa,
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RGA_FORMAT_YCbCr_420_P = 0xb,
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RGA_FORMAT_YCrCb_422_SP = 0xc,
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RGA_FORMAT_YCrCb_422_P = 0xd,
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RGA_FORMAT_YCrCb_420_SP = 0xe,
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RGA_FORMAT_YCrCb_420_P = 0xf,
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RGA_FORMAT_BPP1 = 0x10,
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RGA_FORMAT_BPP2 = 0x11,
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RGA_FORMAT_BPP4 = 0x12,
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RGA_FORMAT_BPP8 = 0x13,
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RGA_FORMAT_Y4 = 0x14,
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RGA_FORMAT_YCbCr_400 = 0x15,
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RGA_FORMAT_BGRX_8888 = 0x16,
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RGA_FORMAT_YVYU_422 = 0x18,
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RGA_FORMAT_YVYU_420 = 0x19,
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RGA_FORMAT_VYUY_422 = 0x1a,
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RGA_FORMAT_VYUY_420 = 0x1b,
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RGA_FORMAT_YUYV_422 = 0x1c,
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RGA_FORMAT_YUYV_420 = 0x1d,
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RGA_FORMAT_UYVY_422 = 0x1e,
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RGA_FORMAT_UYVY_420 = 0x1f,
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RGA_FORMAT_YCbCr_420_SP_10B = 0x20,
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RGA_FORMAT_YCrCb_420_SP_10B = 0x21,
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RGA_FORMAT_YCbCr_422_SP_10B = 0x22,
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RGA_FORMAT_YCrCb_422_SP_10B = 0x23,
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RGA_FORMAT_BGR_565 = 0x24,
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RGA_FORMAT_BGRA_5551 = 0x25,
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RGA_FORMAT_BGRA_4444 = 0x26,
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RGA_FORMAT_ARGB_8888 = 0x28,
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RGA_FORMAT_XRGB_8888 = 0x29,
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RGA_FORMAT_ARGB_5551 = 0x2a,
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RGA_FORMAT_ARGB_4444 = 0x2b,
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RGA_FORMAT_ABGR_8888 = 0x2c,
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RGA_FORMAT_XBGR_8888 = 0x2d,
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RGA_FORMAT_ABGR_5551 = 0x2e,
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RGA_FORMAT_ABGR_4444 = 0x2f,
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RGA_FORMAT_RGBA_2BPP = 0x30,
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RGA_FORMAT_UNKNOWN = 0x100,
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};
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enum rga_alpha_mode {
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RGA_ALPHA_STRAIGHT = 0,
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RGA_ALPHA_INVERSE = 1,
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};
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enum rga_global_blend_mode {
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RGA_ALPHA_GLOBAL = 0,
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RGA_ALPHA_PER_PIXEL = 1,
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RGA_ALPHA_PER_PIXEL_GLOBAL = 2,
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};
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enum rga_alpha_cal_mode {
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RGA_ALPHA_SATURATION = 0,
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RGA_ALPHA_NO_SATURATION = 1,
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};
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enum rga_factor_mode {
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RGA_ALPHA_ZERO = 0,
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RGA_ALPHA_ONE = 1,
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/*
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* When used as a factor for the SRC channel, it indicates
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* the use of the DST channel's alpha value, and vice versa.
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*/
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RGA_ALPHA_OPPOSITE = 2,
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RGA_ALPHA_OPPOSITE_INVERSE = 3,
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RGA_ALPHA_OWN = 4,
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};
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enum rga_color_mode {
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RGA_ALPHA_PRE_MULTIPLIED = 0,
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RGA_ALPHA_NO_PRE_MULTIPLIED = 1,
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};
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enum rga_alpha_blend_mode {
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RGA_ALPHA_NONE = 0,
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RGA_ALPHA_BLEND_SRC,
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RGA_ALPHA_BLEND_DST,
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RGA_ALPHA_BLEND_SRC_OVER,
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RGA_ALPHA_BLEND_DST_OVER,
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RGA_ALPHA_BLEND_SRC_IN,
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RGA_ALPHA_BLEND_DST_IN,
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RGA_ALPHA_BLEND_SRC_OUT,
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RGA_ALPHA_BLEND_DST_OUT,
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RGA_ALPHA_BLEND_SRC_ATOP,
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RGA_ALPHA_BLEND_DST_ATOP,
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RGA_ALPHA_BLEND_XOR,
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RGA_ALPHA_BLEND_CLEAR,
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};
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#define RGA_SCHED_PRIORITY_DEFAULT 0
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#define RGA_SCHED_PRIORITY_MAX 6
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#define RGA_VERSION_SIZE 16
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#define RGA_HW_SIZE 5
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struct rga_version_t {
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uint32_t major;
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uint32_t minor;
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uint32_t revision;
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uint8_t str[RGA_VERSION_SIZE];
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};
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struct rga_hw_versions_t {
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struct rga_version_t version[RGA_HW_SIZE];
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uint32_t size;
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};
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struct rga_memory_parm {
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uint32_t width;
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uint32_t height;
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uint32_t format;
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uint32_t size;
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};
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struct rga_external_buffer {
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uint64_t memory;
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uint32_t type;
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uint32_t handle;
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struct rga_memory_parm memory_parm;
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uint8_t reserve[252];
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};
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struct rga_buffer_pool {
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uint64_t buffers_ptr;
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uint32_t size;
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};
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struct rga_mmu_info_t {
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unsigned long src0_base_addr;
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unsigned long src1_base_addr;
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unsigned long dst_base_addr;
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unsigned long els_base_addr;
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/* [0] mmu enable [1] flush [2] prefetch_en [3] prefetch dir */
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u8 src0_mmu_flag;
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u8 src1_mmu_flag;
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u8 dst_mmu_flag;
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u8 els_mmu_flag;
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};
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struct rga_color_fill_t {
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int16_t gr_x_a;
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int16_t gr_y_a;
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int16_t gr_x_b;
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int16_t gr_y_b;
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int16_t gr_x_g;
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int16_t gr_y_g;
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int16_t gr_x_r;
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int16_t gr_y_r;
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};
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/***************************************/
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/* porting from rga.h for msg convert */
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/***************************************/
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struct rga_fading_t {
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uint8_t b;
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uint8_t g;
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uint8_t r;
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uint8_t res;
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};
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struct rga_mmu_t {
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uint8_t mmu_en;
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uint64_t base_addr;
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/*
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* [0] mmu enable [1] src_flush [2] dst_flush
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* [3] CMD_flush [4~5] page size
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*/
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uint32_t mmu_flag;
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};
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struct rga_rect_t {
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uint16_t xmin;
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/* width - 1 */
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uint16_t xmax;
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uint16_t ymin;
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/* height - 1 */
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uint16_t ymax;
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};
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struct rga_point_t {
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uint16_t x;
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uint16_t y;
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};
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struct rga_line_draw_t {
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/* LineDraw_start_point */
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struct rga_point_t start_point;
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/* LineDraw_end_point */
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struct rga_point_t end_point;
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/* LineDraw_color */
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uint32_t color;
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/* (enum) LineDrawing mode sel */
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uint32_t flag;
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/* range 1~16 */
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uint32_t line_width;
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};
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/* color space convert coefficient. */
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struct rga_csc_coe {
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int16_t r_v;
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int16_t g_y;
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int16_t b_u;
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int32_t off;
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};
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struct rga_full_csc {
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uint8_t flag;
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struct rga_csc_coe coe_y;
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struct rga_csc_coe coe_u;
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struct rga_csc_coe coe_v;
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};
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struct rga_csc_range {
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uint16_t max;
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uint16_t min;
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};
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struct rga_csc_clip {
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struct rga_csc_range y;
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struct rga_csc_range uv;
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};
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struct rga_mosaic_info {
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uint8_t enable;
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uint8_t mode;
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};
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/* MAX(min, (max - channel_value)) */
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struct rga_osd_invert_factor {
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uint8_t alpha_max;
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uint8_t alpha_min;
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uint8_t yg_max;
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uint8_t yg_min;
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uint8_t crb_max;
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uint8_t crb_min;
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};
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struct rga_color {
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union {
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struct {
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uint8_t red;
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uint8_t green;
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uint8_t blue;
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uint8_t alpha;
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};
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uint32_t value;
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};
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};
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struct rga_osd_bpp2 {
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uint8_t ac_swap; // ac swap flag
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// 0: CA
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// 1: AC
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uint8_t endian_swap; // rgba2bpp endian swap
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// 0: Big endian
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// 1: Little endian
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struct rga_color color0;
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struct rga_color color1;
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};
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struct rga_osd_mode_ctrl {
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uint8_t mode; // OSD cal mode:
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// 0b'1: statistics mode
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// 1b'1: auto inversion overlap mode
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uint8_t direction_mode; // horizontal or vertical
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// 0: horizontal
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// 1: vertical
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uint8_t width_mode; // using @fix_width or LUT width
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// 0: fix width
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// 1: LUT width
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uint16_t block_fix_width; // OSD block fixed width
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// real width = (fix_width + 1) * 2
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uint8_t block_num; // OSD block num
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uint16_t flags_index; // auto invert flags index
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/* invertion config */
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uint8_t color_mode; // selete color
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// 0: src1 color
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// 1: config data color
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uint8_t invert_flags_mode; // invert flag selete
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// 0: use RAM flag
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// 1: usr last result
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uint8_t default_color_sel; // default color mode
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// 0: default is bright
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// 1: default is dark
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uint8_t invert_enable; // invert channel enable
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// 1 << 0: alpha enable
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// 1 << 1: Y/G disable
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// 1 << 3: C/RB disable
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uint8_t invert_mode; // invert cal mode
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// 0: normal(max-data)
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// 1: swap
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uint8_t invert_thresh; // if luma > thresh, osd_flag to be 1
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uint8_t unfix_index; // OSD width config index
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};
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struct rga_osd_info {
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uint8_t enable;
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struct rga_osd_mode_ctrl mode_ctrl;
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struct rga_osd_invert_factor cal_factor;
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struct rga_osd_bpp2 bpp2_info;
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union {
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struct {
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uint32_t last_flags0;
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uint32_t last_flags1;
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};
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uint64_t last_flags;
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};
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union {
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struct {
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uint32_t cur_flags0;
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uint32_t cur_flags1;
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};
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uint64_t cur_flags;
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};
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};
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struct rga_pre_intr_info {
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uint8_t enable;
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uint8_t read_intr_en;
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uint8_t write_intr_en;
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uint8_t read_hold_en;
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uint32_t read_threshold;
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uint32_t write_start;
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uint32_t write_step;
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};
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struct rga_win_info_t {
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/* yrgb mem addr */
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unsigned long yrgb_addr;
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/* cb/cr mem addr */
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unsigned long uv_addr;
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/* cr mem addr */
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unsigned long v_addr;
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/* definition by RK_FORMAT */
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unsigned int format;
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unsigned short src_act_w;
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unsigned short src_act_h;
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unsigned short dst_act_w;
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unsigned short dst_act_h;
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unsigned short x_offset;
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unsigned short y_offset;
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unsigned short vir_w;
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unsigned short vir_h;
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unsigned short y2r_mode;
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unsigned short r2y_mode;
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unsigned short rotate_mode;
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/* RASTER or FBCD or TILE */
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unsigned short rd_mode;
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unsigned short is_10b_compact;
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unsigned short is_10b_endian;
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unsigned short enable;
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};
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struct rga_img_info_t {
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/* yrgb mem addr */
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uint64_t yrgb_addr;
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/* cb/cr mem addr */
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uint64_t uv_addr;
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/* cr mem addr */
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uint64_t v_addr;
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/* definition by RK_FORMAT */
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uint32_t format;
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uint16_t act_w;
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uint16_t act_h;
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uint16_t x_offset;
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uint16_t y_offset;
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uint16_t vir_w;
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uint16_t vir_h;
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uint16_t endian_mode;
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/* useless */
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uint16_t alpha_swap;
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/* used by RGA3 */
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uint16_t rotate_mode;
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uint16_t rd_mode;
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uint16_t compact_mode;
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uint16_t is_10b_endian;
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uint16_t enable;
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};
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struct rga_feature {
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uint32_t global_alpha_en:1;
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uint32_t full_csc_clip_en:1;
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uint32_t user_close_fence:1;
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};
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struct rga_req {
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/* (enum) process mode sel */
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uint8_t render_mode;
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struct rga_img_info_t src;
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struct rga_img_info_t dst;
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struct rga_img_info_t pat;
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/* rop4 mask addr */
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uint64_t rop_mask_addr;
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/* LUT addr */
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uint64_t LUT_addr;
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/* dst clip window default value is dst_vir */
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/* value from [0, w-1] / [0, h-1]*/
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struct rga_rect_t clip;
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/* dst angle default value 0 16.16 scan from table */
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int32_t sina;
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/* dst angle default value 0 16.16 scan from table */
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int32_t cosa;
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/* alpha rop process flag */
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/* ([0] = 1 alpha_rop_enable) */
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/* ([1] = 1 rop enable) */
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/* ([2] = 1 fading_enable) */
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/* ([3] = 1 PD_enable) */
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/* ([4] = 1 alpha cal_mode_sel) */
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/* ([5] = 1 dither_enable) */
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/* ([6] = 1 gradient fill mode sel) */
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/* ([7] = 1 AA_enable) */
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uint16_t alpha_rop_flag;
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/* 0 nearst / 1 bilnear / 2 bicubic */
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uint8_t scale_mode;
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/* color key max */
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uint32_t color_key_max;
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/* color key min */
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uint32_t color_key_min;
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/* foreground color */
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uint32_t fg_color;
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/* background color */
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uint32_t bg_color;
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/* color fill use gradient */
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struct rga_color_fill_t gr_color;
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struct rga_line_draw_t line_draw_info;
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struct rga_fading_t fading;
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/* porter duff alpha mode sel */
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uint8_t PD_mode;
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/* legacy: global alpha value */
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uint8_t alpha_global_value;
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/* rop2/3/4 code scan from rop code table*/
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uint16_t rop_code;
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/* [2] 0 blur 1 sharp / [1:0] filter_type*/
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uint8_t bsfilter_flag;
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/* (enum) color palette 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
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uint8_t palette_mode;
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/* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
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uint8_t yuv2rgb_mode;
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/* 0/big endian 1/little endian*/
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uint8_t endian_mode;
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/* (enum) rotate mode */
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/* 0x0, no rotate */
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/* 0x1, rotate */
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/* 0x2, x_mirror */
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/* 0x3, y_mirror */
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uint8_t rotate_mode;
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/* 0 solid color / 1 pattern color */
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uint8_t color_fill_mode;
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/* mmu information */
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struct rga_mmu_t mmu_info;
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/* ([0~1] alpha mode) */
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/* ([2~3] rop mode) */
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/* ([4] zero mode en) */
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/* ([5] dst alpha mode) */
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/* ([6] alpha output mode sel) 0 src / 1 dst*/
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uint8_t alpha_rop_mode;
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uint8_t src_trans_mode;
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uint8_t dither_mode;
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/* full color space convert */
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struct rga_full_csc full_csc;
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int32_t in_fence_fd;
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uint8_t core;
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uint8_t priority;
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int32_t out_fence_fd;
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uint8_t handle_flag;
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/* RGA2 1106 add */
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struct rga_mosaic_info mosaic_info;
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uint8_t uvhds_mode;
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uint8_t uvvds_mode;
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struct rga_osd_info osd_info;
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struct rga_pre_intr_info pre_intr_info;
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/* global alpha */
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uint8_t fg_global_alpha;
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uint8_t bg_global_alpha;
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struct rga_feature feature;
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struct rga_csc_clip full_csc_clip;
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uint8_t reservr[43];
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};
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struct rga_alpha_config {
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bool enable;
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bool fg_pre_multiplied;
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bool bg_pre_multiplied;
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bool fg_pixel_alpha_en;
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bool bg_pixel_alpha_en;
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bool fg_global_alpha_en;
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bool bg_global_alpha_en;
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uint16_t fg_global_alpha_value;
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uint16_t bg_global_alpha_value;
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enum rga_alpha_blend_mode mode;
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};
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struct rga2_req {
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/* (enum) process mode sel */
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u8 render_mode;
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/* active window */
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struct rga_img_info_t src;
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struct rga_img_info_t src1;
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struct rga_img_info_t dst;
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struct rga_img_info_t pat;
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/* rop4 mask addr */
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unsigned long rop_mask_addr;
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/* LUT addr */
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unsigned long LUT_addr;
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u32 rop_mask_stride;
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/* 0: SRC + DST => DST */
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/* 1: SRC + SRC1 => DST */
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u8 bitblt_mode;
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/* [1:0] */
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/* 0 degree 0x0 */
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/* 90 degree 0x1 */
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/* 180 degree 0x2 */
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/* 270 degree 0x3 */
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/* [5:4] */
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/* none 0x0 */
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/* x_mirror 0x1 */
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/* y_mirror 0x2 */
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/* x_mirror + y_mirror 0x3 */
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u8 rotate_mode;
|
|
/* alpha rop process flag */
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/* ([0] = 1 alpha_rop_enable) */
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/* ([1] = 1 rop enable) */
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/* ([2] = 1 fading_enable) */
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/* ([3] = 1 alpha cal_mode_sel) */
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/* ([4] = 1 src_dither_up_enable) */
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/* ([5] = 1 dst_dither_up_enable) */
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/* ([6] = 1 dither_down_enable) */
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/* ([7] = 1 gradient fill mode sel) */
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u16 alpha_rop_flag;
|
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struct rga_alpha_config alpha_config;
|
|
/* 0 1 2 3 */
|
u8 scale_bicu_mode;
|
|
u32 color_key_max;
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u32 color_key_min;
|
|
/* foreground color */
|
u32 fg_color;
|
/* background color */
|
u32 bg_color;
|
|
u8 color_fill_mode;
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/* color fill use gradient */
|
struct rga_color_fill_t gr_color;
|
|
/* Fading value */
|
u8 fading_alpha_value;
|
u8 fading_r_value;
|
u8 fading_g_value;
|
u8 fading_b_value;
|
|
/* src global alpha value */
|
u8 src_a_global_val;
|
/* dst global alpha value */
|
u8 dst_a_global_val;
|
|
/* rop mode select 0 : rop2 1 : rop3 2 : rop4 */
|
u8 rop_mode;
|
/* rop2/3/4 code */
|
u16 rop_code;
|
|
/* (enum) color palette 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
|
u8 palette_mode;
|
|
/* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
|
u8 yuv2rgb_mode;
|
|
u8 full_csc_en;
|
|
/* 0/little endian 1/big endian */
|
u8 endian_mode;
|
|
u8 CMD_fin_int_enable;
|
|
/* mmu information */
|
struct rga_mmu_info_t mmu_info;
|
|
u8 alpha_zero_key;
|
u8 src_trans_mode;
|
|
/* useless */
|
u8 alpha_swp;
|
u8 dither_mode;
|
|
u8 rgb2yuv_mode;
|
|
/* RGA2 1106 add */
|
struct rga_mosaic_info mosaic_info;
|
|
uint8_t yin_yout_en;
|
|
uint8_t uvhds_mode;
|
uint8_t uvvds_mode;
|
|
struct rga_osd_info osd_info;
|
};
|
|
struct rga3_req {
|
/* (enum) process mode sel */
|
u8 render_mode;
|
|
struct rga_win_info_t win0;
|
struct rga_win_info_t wr;
|
struct rga_win_info_t win1;
|
|
/* rop4 mask addr */
|
unsigned long rop_mask_addr;
|
unsigned long LUT_addr;
|
|
u32 rop_mask_stride;
|
|
u8 bitblt_mode;
|
u8 rotate_mode;
|
|
u16 alpha_rop_flag;
|
|
struct rga_alpha_config alpha_config;
|
|
/* for abb mode presever alpha. */
|
bool abb_alpha_pass;
|
|
u8 scale_bicu_mode;
|
|
u32 color_key_max;
|
u32 color_key_min;
|
|
u32 fg_color;
|
u32 bg_color;
|
|
u8 color_fill_mode;
|
struct rga_color_fill_t gr_color;
|
|
u8 fading_alpha_value;
|
u8 fading_r_value;
|
u8 fading_g_value;
|
u8 fading_b_value;
|
|
/* win0 global alpha value */
|
u8 win0_a_global_val;
|
/* win1 global alpha value */
|
u8 win1_a_global_val;
|
|
u8 rop_mode;
|
u16 rop_code;
|
|
u8 palette_mode;
|
|
u8 yuv2rgb_mode;
|
|
u8 endian_mode;
|
|
u8 CMD_fin_int_enable;
|
|
struct rga_mmu_info_t mmu_info;
|
|
u8 alpha_zero_key;
|
u8 src_trans_mode;
|
|
u8 alpha_swp;
|
u8 dither_mode;
|
|
u8 rgb2yuv_mode;
|
};
|
|
struct rga_video_frame_info {
|
uint32_t x_offset;
|
uint32_t y_offset;
|
uint32_t width;
|
uint32_t height;
|
uint32_t format;
|
uint32_t vir_w;
|
uint32_t vir_h;
|
uint32_t rd_mode;
|
};
|
|
struct rga_mpi_job_t {
|
struct dma_buf *dma_buf_src0;
|
struct dma_buf *dma_buf_src1;
|
struct dma_buf *dma_buf_dst;
|
|
struct rga_video_frame_info *src;
|
struct rga_video_frame_info *pat;
|
struct rga_video_frame_info *dst;
|
struct rga_video_frame_info *output;
|
|
int ctx_id;
|
};
|
|
struct rga_user_request {
|
uint64_t task_ptr;
|
uint32_t task_num;
|
uint32_t id;
|
uint32_t sync_mode;
|
uint32_t release_fence_fd;
|
|
uint32_t mpi_config_flags;
|
|
uint32_t acquire_fence_fd;
|
|
uint8_t reservr[120];
|
};
|
|
int rga_mpi_commit(struct rga_mpi_job_t *mpi_job);
|
|
#endif /*_RGA_DRIVER_H_*/
|
