// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
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*
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* author:
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* Ding Wei, leo.ding@rock-chips.com
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*
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include <soc/rockchip/pm_domains.h>
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#include "../mpp_debug.h"
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#include "../mpp_common.h"
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#include "../mpp_iommu.h"
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#include "mpp_hack_px30.h"
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#include <soc/rockchip/rockchip_iommu.h>
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#define RK_MMU_DTE_ADDR 0x00 /* Directory table address */
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#define RK_MMU_STATUS 0x04
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#define RK_MMU_COMMAND 0x08
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#define RK_MMU_INT_MASK 0x1C /* IRQ enable */
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/* RK_MMU_COMMAND command values */
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#define RK_MMU_CMD_ENABLE_PAGING 0 /* Enable memory translation */
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#define RK_MMU_CMD_DISABLE_PAGING 1 /* Disable memory translation */
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#define RK_MMU_CMD_ENABLE_STALL 2 /* Stall paging to allow other cmds */
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#define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
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#define RK_MMU_CMD_ZAP_CACHE 4 /* Shoot down entire IOTLB */
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#define RK_MMU_CMD_PAGE_FAULT_DONE 5 /* Clear page fault */
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#define RK_MMU_CMD_FORCE_RESET 6 /* Reset all registers */
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/* RK_MMU_INT_* register fields */
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#define RK_MMU_IRQ_MASK 0x03
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/* RK_MMU_STATUS fields */
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#define RK_MMU_STATUS_PAGING_ENABLED BIT(0)
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#define RK_MMU_STATUS_STALL_ACTIVE BIT(2)
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static bool mpp_iommu_is_paged(struct mpp_rk_iommu *iommu)
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{
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int i;
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u32 status;
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bool active = true;
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for (i = 0; i < iommu->mmu_num; i++) {
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status = readl(iommu->bases[i] + RK_MMU_STATUS);
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active &= !!(status & RK_MMU_STATUS_PAGING_ENABLED);
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}
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return active;
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}
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static u32 mpp_iommu_get_dte_addr(struct mpp_rk_iommu *iommu)
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{
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return readl(iommu->bases[0] + RK_MMU_DTE_ADDR);
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}
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static int mpp_iommu_enable(struct mpp_rk_iommu *iommu)
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{
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int i;
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/* check iommu whether is paged */
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iommu->is_paged = mpp_iommu_is_paged(iommu);
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if (iommu->is_paged)
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return 0;
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/* enable stall */
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for (i = 0; i < iommu->mmu_num; i++)
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writel(RK_MMU_CMD_ENABLE_STALL,
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iommu->bases[i] + RK_MMU_COMMAND);
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udelay(2);
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/* force reset */
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for (i = 0; i < iommu->mmu_num; i++)
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writel(RK_MMU_CMD_FORCE_RESET,
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iommu->bases[i] + RK_MMU_COMMAND);
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udelay(2);
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for (i = 0; i < iommu->mmu_num; i++) {
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/* restore dte and status */
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writel(iommu->dte_addr,
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iommu->bases[i] + RK_MMU_DTE_ADDR);
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/* zap cache */
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writel(RK_MMU_CMD_ZAP_CACHE,
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iommu->bases[i] + RK_MMU_COMMAND);
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/* irq mask */
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writel(RK_MMU_IRQ_MASK,
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iommu->bases[i] + RK_MMU_INT_MASK);
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}
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udelay(2);
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/* enable paging */
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for (i = 0; i < iommu->mmu_num; i++)
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writel(RK_MMU_CMD_ENABLE_PAGING,
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iommu->bases[i] + RK_MMU_COMMAND);
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udelay(2);
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/* disable stall */
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for (i = 0; i < iommu->mmu_num; i++)
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writel(RK_MMU_CMD_DISABLE_STALL,
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iommu->bases[i] + RK_MMU_COMMAND);
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udelay(2);
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/* iommu should be paging enable */
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iommu->is_paged = mpp_iommu_is_paged(iommu);
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if (!iommu->is_paged) {
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mpp_err("iommu->base_addr=%08x enable failed\n",
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iommu->base_addr[0]);
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return -EINVAL;
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}
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return 0;
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}
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static int mpp_iommu_disable(struct mpp_rk_iommu *iommu)
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{
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int i;
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u32 dte;
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if (iommu->is_paged) {
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dte = readl(iommu->bases[0] + RK_MMU_DTE_ADDR);
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if (!dte)
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return -EINVAL;
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udelay(2);
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/* enable stall */
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for (i = 0; i < iommu->mmu_num; i++)
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writel(RK_MMU_CMD_ENABLE_STALL,
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iommu->bases[i] + RK_MMU_COMMAND);
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udelay(2);
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/* disable paging */
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for (i = 0; i < iommu->mmu_num; i++)
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writel(RK_MMU_CMD_DISABLE_PAGING,
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iommu->bases[i] + RK_MMU_COMMAND);
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udelay(2);
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/* disable stall */
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for (i = 0; i < iommu->mmu_num; i++)
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writel(RK_MMU_CMD_DISABLE_STALL,
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iommu->bases[i] + RK_MMU_COMMAND);
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udelay(2);
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}
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return 0;
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}
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int px30_workaround_combo_init(struct mpp_dev *mpp)
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{
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struct mpp_rk_iommu *iommu = NULL, *loop = NULL, *n;
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struct platform_device *pdev = mpp->iommu_info->pdev;
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/* find whether exist in iommu link */
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list_for_each_entry_safe(loop, n, &mpp->queue->mmu_list, link) {
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if (loop->base_addr[0] == pdev->resource[0].start) {
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iommu = loop;
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break;
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}
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}
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/* if not exist, add it */
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if (!iommu) {
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int i;
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struct resource *res;
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void __iomem *base;
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iommu = devm_kzalloc(mpp->srv->dev, sizeof(*iommu), GFP_KERNEL);
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for (i = 0; i < pdev->num_resources; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res)
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continue;
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base = devm_ioremap(&pdev->dev,
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res->start, resource_size(res));
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if (IS_ERR(base))
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continue;
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iommu->base_addr[i] = res->start;
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iommu->bases[i] = base;
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iommu->mmu_num++;
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}
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iommu->grf_val = mpp->grf_info->val & MPP_GRF_VAL_MASK;
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if (mpp->hw_ops->clk_on)
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mpp->hw_ops->clk_on(mpp);
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/*
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* ensure that iommu is enable, so that read valid dte value
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*/
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if (rockchip_iommu_is_enabled(mpp->dev))
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iommu->dte_addr = mpp_iommu_get_dte_addr(iommu);
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else {
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rockchip_iommu_enable(mpp->dev);
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iommu->dte_addr = mpp_iommu_get_dte_addr(iommu);
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rockchip_iommu_disable(mpp->dev);
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}
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dev_err(mpp->dev, "%s dte_addr %08x\n", __func__, iommu->dte_addr);
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if (mpp->hw_ops->clk_off)
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mpp->hw_ops->clk_off(mpp);
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INIT_LIST_HEAD(&iommu->link);
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mutex_lock(&mpp->queue->mmu_lock);
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list_add_tail(&iommu->link, &mpp->queue->mmu_list);
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mutex_unlock(&mpp->queue->mmu_lock);
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}
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mpp->iommu_info->iommu = iommu;
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return 0;
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}
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int px30_workaround_combo_switch_grf(struct mpp_dev *mpp)
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{
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int ret = 0;
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u32 curr_val;
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u32 next_val;
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bool pd_is_on;
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struct mpp_rk_iommu *loop = NULL, *n;
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if (!mpp->grf_info->grf || !mpp->grf_info->val)
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return 0;
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curr_val = mpp_get_grf(mpp->grf_info);
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next_val = mpp->grf_info->val & MPP_GRF_VAL_MASK;
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if (curr_val == next_val)
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return 0;
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pd_is_on = rockchip_pmu_pd_is_on(mpp->dev);
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if (!pd_is_on)
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rockchip_pmu_pd_on(mpp->dev);
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mpp->hw_ops->clk_on(mpp);
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list_for_each_entry_safe(loop, n, &mpp->queue->mmu_list, link) {
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/* update iommu parameters */
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if (loop->grf_val == curr_val)
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loop->is_paged = mpp_iommu_is_paged(loop);
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/* disable all iommu */
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mpp_iommu_disable(loop);
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}
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mpp_set_grf(mpp->grf_info);
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/* enable current iommu */
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ret = mpp_iommu_enable(mpp->iommu_info->iommu);
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mpp->hw_ops->clk_off(mpp);
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if (!pd_is_on)
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rockchip_pmu_pd_off(mpp->dev);
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return ret;
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}
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