// SPDX-License-Identifier: GPL-2.0
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/**
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* typec_wcove.c - WhiskeyCove PMIC USB Type-C PHY driver
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*
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* Copyright (C) 2017 Intel Corporation
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* Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
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*/
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#include <linux/acpi.h>
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#include <linux/module.h>
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#include <linux/usb/tcpm.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/intel_soc_pmic.h>
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/* Register offsets */
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#define WCOVE_CHGRIRQ0 0x4e09
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#define USBC_CONTROL1 0x7001
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#define USBC_CONTROL2 0x7002
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#define USBC_CONTROL3 0x7003
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#define USBC_CC1_CTRL 0x7004
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#define USBC_CC2_CTRL 0x7005
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#define USBC_STATUS1 0x7007
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#define USBC_STATUS2 0x7008
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#define USBC_STATUS3 0x7009
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#define USBC_CC1 0x700a
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#define USBC_CC2 0x700b
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#define USBC_CC1_STATUS 0x700c
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#define USBC_CC2_STATUS 0x700d
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#define USBC_IRQ1 0x7015
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#define USBC_IRQ2 0x7016
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#define USBC_IRQMASK1 0x7017
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#define USBC_IRQMASK2 0x7018
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#define USBC_PDCFG2 0x701a
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#define USBC_PDCFG3 0x701b
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#define USBC_PDSTATUS 0x701c
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#define USBC_RXSTATUS 0x701d
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#define USBC_RXINFO 0x701e
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#define USBC_TXCMD 0x701f
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#define USBC_TXINFO 0x7020
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#define USBC_RX_DATA 0x7028
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#define USBC_TX_DATA 0x7047
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/* Register bits */
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#define USBC_CONTROL1_MODE_MASK 0x3
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#define USBC_CONTROL1_MODE_SNK 0
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#define USBC_CONTROL1_MODE_SNKACC 1
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#define USBC_CONTROL1_MODE_SRC 2
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#define USBC_CONTROL1_MODE_SRCACC 3
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#define USBC_CONTROL1_MODE_DRP 4
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#define USBC_CONTROL1_MODE_DRPACC 5
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#define USBC_CONTROL1_MODE_TEST 7
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#define USBC_CONTROL1_CURSRC_MASK 0xc
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#define USBC_CONTROL1_CURSRC_UA_0 (0 << 3)
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#define USBC_CONTROL1_CURSRC_UA_80 (1 << 3)
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#define USBC_CONTROL1_CURSRC_UA_180 (2 << 3)
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#define USBC_CONTROL1_CURSRC_UA_330 (3 << 3)
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#define USBC_CONTROL1_DRPTOGGLE_RANDOM 0xe0
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#define USBC_CONTROL2_UNATT_SNK BIT(0)
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#define USBC_CONTROL2_UNATT_SRC BIT(1)
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#define USBC_CONTROL2_DIS_ST BIT(2)
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#define USBC_CONTROL3_DET_DIS BIT(0)
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#define USBC_CONTROL3_PD_DIS BIT(1)
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#define USBC_CONTROL3_RESETPHY BIT(2)
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#define USBC_CC_CTRL_PU_EN BIT(0)
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#define USBC_CC_CTRL_VCONN_EN BIT(1)
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#define USBC_CC_CTRL_TX_EN BIT(2)
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#define USBC_CC_CTRL_PD_EN BIT(3)
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#define USBC_CC_CTRL_CDET_EN BIT(4)
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#define USBC_CC_CTRL_RDET_EN BIT(5)
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#define USBC_CC_CTRL_ADC_EN BIT(6)
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#define USBC_CC_CTRL_VBUSOK BIT(7)
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#define USBC_STATUS1_DET_ONGOING BIT(6)
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#define USBC_STATUS1_RSLT(r) ((r) & 0xf)
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#define USBC_RSLT_NOTHING 0
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#define USBC_RSLT_SRC_DEFAULT 1
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#define USBC_RSLT_SRC_1_5A 2
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#define USBC_RSLT_SRC_3_0A 3
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#define USBC_RSLT_SNK 4
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#define USBC_RSLT_DEBUG_ACC 5
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#define USBC_RSLT_AUDIO_ACC 6
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#define USBC_RSLT_UNDEF 15
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#define USBC_STATUS1_ORIENT(r) (((r) >> 4) & 0x3)
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#define USBC_ORIENT_NORMAL 1
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#define USBC_ORIENT_REVERSE 2
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#define USBC_STATUS2_VBUS_REQ BIT(5)
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#define UCSC_CC_STATUS_SNK_RP BIT(0)
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#define UCSC_CC_STATUS_PWRDEFSNK BIT(1)
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#define UCSC_CC_STATUS_PWR_1P5A_SNK BIT(2)
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#define UCSC_CC_STATUS_PWR_3A_SNK BIT(3)
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#define UCSC_CC_STATUS_SRC_RP BIT(4)
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#define UCSC_CC_STATUS_RX(r) (((r) >> 5) & 0x3)
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#define USBC_CC_STATUS_RD 1
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#define USBC_CC_STATUS_RA 2
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#define USBC_IRQ1_ADCDONE1 BIT(2)
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#define USBC_IRQ1_OVERTEMP BIT(1)
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#define USBC_IRQ1_SHORT BIT(0)
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#define USBC_IRQ2_CC_CHANGE BIT(7)
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#define USBC_IRQ2_RX_PD BIT(6)
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#define USBC_IRQ2_RX_HR BIT(5)
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#define USBC_IRQ2_RX_CR BIT(4)
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#define USBC_IRQ2_TX_SUCCESS BIT(3)
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#define USBC_IRQ2_TX_FAIL BIT(2)
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#define USBC_IRQMASK1_ALL (USBC_IRQ1_ADCDONE1 | USBC_IRQ1_OVERTEMP | \
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USBC_IRQ1_SHORT)
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#define USBC_IRQMASK2_ALL (USBC_IRQ2_CC_CHANGE | USBC_IRQ2_RX_PD | \
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USBC_IRQ2_RX_HR | USBC_IRQ2_RX_CR | \
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USBC_IRQ2_TX_SUCCESS | USBC_IRQ2_TX_FAIL)
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#define USBC_PDCFG2_SOP BIT(0)
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#define USBC_PDCFG2_SOP_P BIT(1)
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#define USBC_PDCFG2_SOP_PP BIT(2)
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#define USBC_PDCFG2_SOP_P_DEBUG BIT(3)
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#define USBC_PDCFG2_SOP_PP_DEBUG BIT(4)
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#define USBC_PDCFG3_DATAROLE_SHIFT 1
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#define USBC_PDCFG3_SOP_SHIFT 2
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#define USBC_RXSTATUS_RXCLEAR BIT(0)
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#define USBC_RXSTATUS_RXDATA BIT(7)
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#define USBC_RXINFO_RXBYTES(i) (((i) >> 3) & 0x1f)
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#define USBC_TXCMD_BUF_RDY BIT(0)
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#define USBC_TXCMD_START BIT(1)
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#define USBC_TXCMD_NOP (0 << 5)
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#define USBC_TXCMD_MSG (1 << 5)
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#define USBC_TXCMD_CR (2 << 5)
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#define USBC_TXCMD_HR (3 << 5)
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#define USBC_TXCMD_BIST (4 << 5)
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#define USBC_TXINFO_RETRIES(d) (d << 3)
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struct wcove_typec {
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struct mutex lock; /* device lock */
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struct device *dev;
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struct regmap *regmap;
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guid_t guid;
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bool vbus;
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struct tcpc_dev tcpc;
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struct tcpm_port *tcpm;
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};
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#define tcpc_to_wcove(_tcpc_) container_of(_tcpc_, struct wcove_typec, tcpc)
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enum wcove_typec_func {
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WCOVE_FUNC_DRIVE_VBUS = 1,
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WCOVE_FUNC_ORIENTATION,
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WCOVE_FUNC_ROLE,
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WCOVE_FUNC_DRIVE_VCONN,
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};
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enum wcove_typec_orientation {
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WCOVE_ORIENTATION_NORMAL,
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WCOVE_ORIENTATION_REVERSE,
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};
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enum wcove_typec_role {
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WCOVE_ROLE_HOST,
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WCOVE_ROLE_DEVICE,
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};
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#define WCOVE_DSM_UUID "482383f0-2876-4e49-8685-db66211af037"
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static int wcove_typec_func(struct wcove_typec *wcove,
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enum wcove_typec_func func, int param)
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{
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union acpi_object *obj;
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union acpi_object tmp;
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union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
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tmp.type = ACPI_TYPE_INTEGER;
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tmp.integer.value = param;
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obj = acpi_evaluate_dsm(ACPI_HANDLE(wcove->dev), &wcove->guid, 1, func,
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&argv4);
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if (!obj) {
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dev_err(wcove->dev, "%s: failed to evaluate _DSM\n", __func__);
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return -EIO;
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}
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ACPI_FREE(obj);
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return 0;
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}
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static int wcove_init(struct tcpc_dev *tcpc)
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{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
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int ret;
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ret = regmap_write(wcove->regmap, USBC_CONTROL1, 0);
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if (ret)
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return ret;
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/* Unmask everything */
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ret = regmap_write(wcove->regmap, USBC_IRQMASK1, 0);
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if (ret)
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return ret;
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return regmap_write(wcove->regmap, USBC_IRQMASK2, 0);
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}
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static int wcove_get_vbus(struct tcpc_dev *tcpc)
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{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
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unsigned int cc1ctrl;
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int ret;
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ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
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if (ret)
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return ret;
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wcove->vbus = !!(cc1ctrl & USBC_CC_CTRL_VBUSOK);
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return wcove->vbus;
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}
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static int wcove_set_vbus(struct tcpc_dev *tcpc, bool on, bool sink)
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{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
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return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VBUS, on);
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}
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static int wcove_set_vconn(struct tcpc_dev *tcpc, bool on)
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{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
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return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, on);
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}
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static enum typec_cc_status wcove_to_typec_cc(unsigned int cc)
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{
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if (cc & UCSC_CC_STATUS_SNK_RP) {
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if (cc & UCSC_CC_STATUS_PWRDEFSNK)
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return TYPEC_CC_RP_DEF;
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else if (cc & UCSC_CC_STATUS_PWR_1P5A_SNK)
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return TYPEC_CC_RP_1_5;
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else if (cc & UCSC_CC_STATUS_PWR_3A_SNK)
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return TYPEC_CC_RP_3_0;
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} else {
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switch (UCSC_CC_STATUS_RX(cc)) {
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case USBC_CC_STATUS_RD:
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return TYPEC_CC_RD;
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case USBC_CC_STATUS_RA:
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return TYPEC_CC_RA;
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default:
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break;
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}
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}
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return TYPEC_CC_OPEN;
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}
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static int wcove_get_cc(struct tcpc_dev *tcpc, enum typec_cc_status *cc1,
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enum typec_cc_status *cc2)
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{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
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unsigned int cc1_status;
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unsigned int cc2_status;
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int ret;
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ret = regmap_read(wcove->regmap, USBC_CC1_STATUS, &cc1_status);
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if (ret)
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return ret;
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ret = regmap_read(wcove->regmap, USBC_CC2_STATUS, &cc2_status);
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if (ret)
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return ret;
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*cc1 = wcove_to_typec_cc(cc1_status);
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*cc2 = wcove_to_typec_cc(cc2_status);
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return 0;
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}
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static int wcove_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc)
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{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
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unsigned int ctrl;
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switch (cc) {
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case TYPEC_CC_RD:
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ctrl = USBC_CONTROL1_MODE_SNK;
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break;
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case TYPEC_CC_RP_DEF:
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ctrl = USBC_CONTROL1_CURSRC_UA_80 | USBC_CONTROL1_MODE_SRC;
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break;
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case TYPEC_CC_RP_1_5:
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ctrl = USBC_CONTROL1_CURSRC_UA_180 | USBC_CONTROL1_MODE_SRC;
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break;
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case TYPEC_CC_RP_3_0:
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ctrl = USBC_CONTROL1_CURSRC_UA_330 | USBC_CONTROL1_MODE_SRC;
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break;
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case TYPEC_CC_OPEN:
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ctrl = 0;
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break;
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default:
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return -EINVAL;
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}
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return regmap_write(wcove->regmap, USBC_CONTROL1, ctrl);
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}
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static int wcove_set_polarity(struct tcpc_dev *tcpc, enum typec_cc_polarity pol)
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{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
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return wcove_typec_func(wcove, WCOVE_FUNC_ORIENTATION, pol);
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}
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static int wcove_set_current_limit(struct tcpc_dev *tcpc, u32 max_ma, u32 mv)
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{
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return 0;
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}
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static int wcove_set_roles(struct tcpc_dev *tcpc, bool attached,
|
enum typec_role role, enum typec_data_role data)
|
{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
|
unsigned int val;
|
int ret;
|
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ret = wcove_typec_func(wcove, WCOVE_FUNC_ROLE, data == TYPEC_HOST ?
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WCOVE_ROLE_HOST : WCOVE_ROLE_DEVICE);
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if (ret)
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return ret;
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val = role;
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val |= data << USBC_PDCFG3_DATAROLE_SHIFT;
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val |= PD_REV20 << USBC_PDCFG3_SOP_SHIFT;
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return regmap_write(wcove->regmap, USBC_PDCFG3, val);
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}
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static int wcove_set_pd_rx(struct tcpc_dev *tcpc, bool on)
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{
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struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
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return regmap_write(wcove->regmap, USBC_PDCFG2,
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on ? USBC_PDCFG2_SOP : 0);
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}
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static int wcove_pd_transmit(struct tcpc_dev *tcpc,
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enum tcpm_transmit_type type,
|
const struct pd_message *msg,
|
unsigned int negotiated_rev)
|
{
|
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
|
unsigned int info = 0;
|
unsigned int cmd;
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int ret;
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ret = regmap_read(wcove->regmap, USBC_TXCMD, &cmd);
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if (ret)
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return ret;
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|
if (!(cmd & USBC_TXCMD_BUF_RDY)) {
|
dev_warn(wcove->dev, "%s: Last transmission still ongoing!",
|
__func__);
|
return -EBUSY;
|
}
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|
if (msg) {
|
const u8 *data = (void *)msg;
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int i;
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|
for (i = 0; i < pd_header_cnt_le(msg->header) * 4 + 2; i++) {
|
ret = regmap_write(wcove->regmap, USBC_TX_DATA + i,
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data[i]);
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if (ret)
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return ret;
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}
|
}
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|
switch (type) {
|
case TCPC_TX_SOP:
|
case TCPC_TX_SOP_PRIME:
|
case TCPC_TX_SOP_PRIME_PRIME:
|
case TCPC_TX_SOP_DEBUG_PRIME:
|
case TCPC_TX_SOP_DEBUG_PRIME_PRIME:
|
info = type + 1;
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cmd = USBC_TXCMD_MSG;
|
break;
|
case TCPC_TX_HARD_RESET:
|
cmd = USBC_TXCMD_HR;
|
break;
|
case TCPC_TX_CABLE_RESET:
|
cmd = USBC_TXCMD_CR;
|
break;
|
case TCPC_TX_BIST_MODE_2:
|
cmd = USBC_TXCMD_BIST;
|
break;
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default:
|
return -EINVAL;
|
}
|
|
/* NOTE Setting maximum number of retries (7) */
|
ret = regmap_write(wcove->regmap, USBC_TXINFO,
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info | USBC_TXINFO_RETRIES(7));
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if (ret)
|
return ret;
|
|
return regmap_write(wcove->regmap, USBC_TXCMD, cmd | USBC_TXCMD_START);
|
}
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|
static int wcove_start_toggling(struct tcpc_dev *tcpc,
|
enum typec_port_type port_type,
|
enum typec_cc_status cc)
|
{
|
struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
|
unsigned int usbc_ctrl;
|
|
if (port_type != TYPEC_PORT_DRP)
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return -EOPNOTSUPP;
|
|
usbc_ctrl = USBC_CONTROL1_MODE_DRP | USBC_CONTROL1_DRPTOGGLE_RANDOM;
|
|
switch (cc) {
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case TYPEC_CC_RP_1_5:
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usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_180;
|
break;
|
case TYPEC_CC_RP_3_0:
|
usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_330;
|
break;
|
default:
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usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_80;
|
break;
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}
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return regmap_write(wcove->regmap, USBC_CONTROL1, usbc_ctrl);
|
}
|
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static int wcove_read_rx_buffer(struct wcove_typec *wcove, void *msg)
|
{
|
unsigned int info;
|
int ret;
|
int i;
|
|
ret = regmap_read(wcove->regmap, USBC_RXINFO, &info);
|
if (ret)
|
return ret;
|
|
/* FIXME: Check that USBC_RXINFO_RXBYTES(info) matches the header */
|
|
for (i = 0; i < USBC_RXINFO_RXBYTES(info); i++) {
|
ret = regmap_read(wcove->regmap, USBC_RX_DATA + i, msg + i);
|
if (ret)
|
return ret;
|
}
|
|
return regmap_write(wcove->regmap, USBC_RXSTATUS,
|
USBC_RXSTATUS_RXCLEAR);
|
}
|
|
static irqreturn_t wcove_typec_irq(int irq, void *data)
|
{
|
struct wcove_typec *wcove = data;
|
unsigned int usbc_irq1 = 0;
|
unsigned int usbc_irq2 = 0;
|
unsigned int cc1ctrl;
|
int ret;
|
|
mutex_lock(&wcove->lock);
|
|
/* Read.. */
|
ret = regmap_read(wcove->regmap, USBC_IRQ1, &usbc_irq1);
|
if (ret)
|
goto err;
|
|
ret = regmap_read(wcove->regmap, USBC_IRQ2, &usbc_irq2);
|
if (ret)
|
goto err;
|
|
ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
|
if (ret)
|
goto err;
|
|
if (!wcove->tcpm)
|
goto err;
|
|
/* ..check.. */
|
if (usbc_irq1 & USBC_IRQ1_OVERTEMP) {
|
dev_err(wcove->dev, "VCONN Switch Over Temperature!\n");
|
wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, false);
|
/* REVISIT: Report an error? */
|
}
|
|
if (usbc_irq1 & USBC_IRQ1_SHORT) {
|
dev_err(wcove->dev, "VCONN Switch Short Circuit!\n");
|
wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, false);
|
/* REVISIT: Report an error? */
|
}
|
|
if (wcove->vbus != !!(cc1ctrl & USBC_CC_CTRL_VBUSOK))
|
tcpm_vbus_change(wcove->tcpm);
|
|
/* REVISIT: See if tcpm code can be made to consider Type-C HW FSMs */
|
if (usbc_irq2 & USBC_IRQ2_CC_CHANGE)
|
tcpm_cc_change(wcove->tcpm);
|
|
if (usbc_irq2 & USBC_IRQ2_RX_PD) {
|
unsigned int status;
|
|
/*
|
* FIXME: Need to check if TX is ongoing and report
|
* TX_DIREGARDED if needed?
|
*/
|
|
ret = regmap_read(wcove->regmap, USBC_RXSTATUS, &status);
|
if (ret)
|
goto err;
|
|
/* Flush all buffers */
|
while (status & USBC_RXSTATUS_RXDATA) {
|
struct pd_message msg;
|
|
ret = wcove_read_rx_buffer(wcove, &msg);
|
if (ret) {
|
dev_err(wcove->dev, "%s: RX read failed\n",
|
__func__);
|
goto err;
|
}
|
|
tcpm_pd_receive(wcove->tcpm, &msg);
|
|
ret = regmap_read(wcove->regmap, USBC_RXSTATUS,
|
&status);
|
if (ret)
|
goto err;
|
}
|
}
|
|
if (usbc_irq2 & USBC_IRQ2_RX_HR)
|
tcpm_pd_hard_reset(wcove->tcpm);
|
|
/* REVISIT: if (usbc_irq2 & USBC_IRQ2_RX_CR) */
|
|
if (usbc_irq2 & USBC_IRQ2_TX_SUCCESS)
|
tcpm_pd_transmit_complete(wcove->tcpm, TCPC_TX_SUCCESS);
|
|
if (usbc_irq2 & USBC_IRQ2_TX_FAIL)
|
tcpm_pd_transmit_complete(wcove->tcpm, TCPC_TX_FAILED);
|
|
err:
|
/* ..and clear. */
|
if (usbc_irq1) {
|
ret = regmap_write(wcove->regmap, USBC_IRQ1, usbc_irq1);
|
if (ret)
|
dev_WARN(wcove->dev, "%s failed to clear IRQ1\n",
|
__func__);
|
}
|
|
if (usbc_irq2) {
|
ret = regmap_write(wcove->regmap, USBC_IRQ2, usbc_irq2);
|
if (ret)
|
dev_WARN(wcove->dev, "%s failed to clear IRQ2\n",
|
__func__);
|
}
|
|
/* REVISIT: Clear WhiskeyCove CHGR Type-C interrupt */
|
regmap_write(wcove->regmap, WCOVE_CHGRIRQ0, BIT(5));
|
|
mutex_unlock(&wcove->lock);
|
return IRQ_HANDLED;
|
}
|
|
/*
|
* The following power levels should be safe to use with Joule board.
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*/
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static const u32 src_pdo[] = {
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PDO_FIXED(5000, 1500, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |
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PDO_FIXED_USB_COMM),
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};
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static const u32 snk_pdo[] = {
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PDO_FIXED(5000, 500, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |
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PDO_FIXED_USB_COMM),
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PDO_VAR(5000, 12000, 3000),
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};
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static const struct property_entry wcove_props[] = {
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PROPERTY_ENTRY_STRING("data-role", "dual"),
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PROPERTY_ENTRY_STRING("power-role", "dual"),
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PROPERTY_ENTRY_STRING("try-power-role", "sink"),
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PROPERTY_ENTRY_U32_ARRAY("source-pdos", src_pdo),
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PROPERTY_ENTRY_U32_ARRAY("sink-pdos", snk_pdo),
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PROPERTY_ENTRY_U32("op-sink-microwatt", 15000000),
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{ }
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};
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static int wcove_typec_probe(struct platform_device *pdev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
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struct wcove_typec *wcove;
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int irq;
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int ret;
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wcove = devm_kzalloc(&pdev->dev, sizeof(*wcove), GFP_KERNEL);
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if (!wcove)
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return -ENOMEM;
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mutex_init(&wcove->lock);
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wcove->dev = &pdev->dev;
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wcove->regmap = pmic->regmap;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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irq = regmap_irq_get_virq(pmic->irq_chip_data_chgr, irq);
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if (irq < 0)
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return irq;
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ret = guid_parse(WCOVE_DSM_UUID, &wcove->guid);
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if (ret)
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return ret;
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if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &wcove->guid, 0, 0x1f)) {
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dev_err(&pdev->dev, "Missing _DSM functions\n");
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return -ENODEV;
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}
|
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wcove->tcpc.init = wcove_init;
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wcove->tcpc.get_vbus = wcove_get_vbus;
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wcove->tcpc.set_vbus = wcove_set_vbus;
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wcove->tcpc.set_cc = wcove_set_cc;
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wcove->tcpc.get_cc = wcove_get_cc;
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wcove->tcpc.set_polarity = wcove_set_polarity;
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wcove->tcpc.set_vconn = wcove_set_vconn;
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wcove->tcpc.set_current_limit = wcove_set_current_limit;
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wcove->tcpc.start_toggling = wcove_start_toggling;
|
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wcove->tcpc.set_pd_rx = wcove_set_pd_rx;
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wcove->tcpc.set_roles = wcove_set_roles;
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wcove->tcpc.pd_transmit = wcove_pd_transmit;
|
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wcove->tcpc.fwnode = fwnode_create_software_node(wcove_props, NULL);
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if (IS_ERR(wcove->tcpc.fwnode))
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return PTR_ERR(wcove->tcpc.fwnode);
|
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wcove->tcpm = tcpm_register_port(wcove->dev, &wcove->tcpc);
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if (IS_ERR(wcove->tcpm)) {
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fwnode_remove_software_node(wcove->tcpc.fwnode);
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return PTR_ERR(wcove->tcpm);
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}
|
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ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
|
wcove_typec_irq, IRQF_ONESHOT,
|
"wcove_typec", wcove);
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if (ret) {
|
tcpm_unregister_port(wcove->tcpm);
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fwnode_remove_software_node(wcove->tcpc.fwnode);
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return ret;
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}
|
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platform_set_drvdata(pdev, wcove);
|
return 0;
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}
|
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static int wcove_typec_remove(struct platform_device *pdev)
|
{
|
struct wcove_typec *wcove = platform_get_drvdata(pdev);
|
unsigned int val;
|
|
/* Mask everything */
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regmap_read(wcove->regmap, USBC_IRQMASK1, &val);
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regmap_write(wcove->regmap, USBC_IRQMASK1, val | USBC_IRQMASK1_ALL);
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regmap_read(wcove->regmap, USBC_IRQMASK2, &val);
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regmap_write(wcove->regmap, USBC_IRQMASK2, val | USBC_IRQMASK2_ALL);
|
|
tcpm_unregister_port(wcove->tcpm);
|
fwnode_remove_software_node(wcove->tcpc.fwnode);
|
|
return 0;
|
}
|
|
static struct platform_driver wcove_typec_driver = {
|
.driver = {
|
.name = "bxt_wcove_usbc",
|
},
|
.probe = wcove_typec_probe,
|
.remove = wcove_typec_remove,
|
};
|
|
module_platform_driver(wcove_typec_driver);
|
|
MODULE_AUTHOR("Intel Corporation");
|
MODULE_LICENSE("GPL v2");
|
MODULE_DESCRIPTION("WhiskeyCove PMIC USB Type-C PHY driver");
|
MODULE_ALIAS("platform:bxt_wcove_usbc");
|
