/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_FOTG210_H
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#define __LINUX_FOTG210_H
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#include <linux/usb/ehci-dbgp.h>
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/* definitions used for the EHCI driver */
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/*
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* __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
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* __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
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* the host controller implementation.
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*
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* To facilitate the strongest possible byte-order checking from "sparse"
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* and so on, we use __leXX unless that's not practical.
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*/
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#define __hc32 __le32
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#define __hc16 __le16
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/* statistics can be kept for tuning/monitoring */
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struct fotg210_stats {
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/* irq usage */
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unsigned long normal;
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unsigned long error;
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unsigned long iaa;
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unsigned long lost_iaa;
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/* termination of urbs from core */
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unsigned long complete;
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unsigned long unlink;
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};
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/* fotg210_hcd->lock guards shared data against other CPUs:
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* fotg210_hcd: async, unlink, periodic (and shadow), ...
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* usb_host_endpoint: hcpriv
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* fotg210_qh: qh_next, qtd_list
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* fotg210_qtd: qtd_list
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*
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* Also, hold this lock when talking to HC registers or
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* when updating hw_* fields in shared qh/qtd/... structures.
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*/
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#define FOTG210_MAX_ROOT_PORTS 1 /* see HCS_N_PORTS */
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/*
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* fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
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* controller may be doing DMA. Lower values mean there's no DMA.
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*/
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enum fotg210_rh_state {
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FOTG210_RH_HALTED,
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FOTG210_RH_SUSPENDED,
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FOTG210_RH_RUNNING,
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FOTG210_RH_STOPPING
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};
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/*
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* Timer events, ordered by increasing delay length.
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* Always update event_delays_ns[] and event_handlers[] (defined in
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* ehci-timer.c) in parallel with this list.
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*/
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enum fotg210_hrtimer_event {
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FOTG210_HRTIMER_POLL_ASS, /* Poll for async schedule off */
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FOTG210_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
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FOTG210_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
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FOTG210_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
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FOTG210_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
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FOTG210_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
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FOTG210_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
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FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
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FOTG210_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
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FOTG210_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
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FOTG210_HRTIMER_NUM_EVENTS /* Must come last */
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};
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#define FOTG210_HRTIMER_NO_EVENT 99
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struct fotg210_hcd { /* one per controller */
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/* timing support */
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enum fotg210_hrtimer_event next_hrtimer_event;
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unsigned enabled_hrtimer_events;
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ktime_t hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
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struct hrtimer hrtimer;
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int PSS_poll_count;
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int ASS_poll_count;
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int died_poll_count;
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/* glue to PCI and HCD framework */
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struct fotg210_caps __iomem *caps;
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struct fotg210_regs __iomem *regs;
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struct ehci_dbg_port __iomem *debug;
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__u32 hcs_params; /* cached register copy */
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spinlock_t lock;
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enum fotg210_rh_state rh_state;
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/* general schedule support */
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bool scanning:1;
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bool need_rescan:1;
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bool intr_unlinking:1;
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bool async_unlinking:1;
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bool shutdown:1;
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struct fotg210_qh *qh_scan_next;
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/* async schedule support */
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struct fotg210_qh *async;
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struct fotg210_qh *dummy; /* For AMD quirk use */
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struct fotg210_qh *async_unlink;
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struct fotg210_qh *async_unlink_last;
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struct fotg210_qh *async_iaa;
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unsigned async_unlink_cycle;
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unsigned async_count; /* async activity count */
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/* periodic schedule support */
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#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
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unsigned periodic_size;
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__hc32 *periodic; /* hw periodic table */
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dma_addr_t periodic_dma;
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struct list_head intr_qh_list;
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unsigned i_thresh; /* uframes HC might cache */
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union fotg210_shadow *pshadow; /* mirror hw periodic table */
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struct fotg210_qh *intr_unlink;
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struct fotg210_qh *intr_unlink_last;
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unsigned intr_unlink_cycle;
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unsigned now_frame; /* frame from HC hardware */
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unsigned next_frame; /* scan periodic, start here */
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unsigned intr_count; /* intr activity count */
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unsigned isoc_count; /* isoc activity count */
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unsigned periodic_count; /* periodic activity count */
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/* max periodic time per uframe */
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unsigned uframe_periodic_max;
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/* list of itds completed while now_frame was still active */
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struct list_head cached_itd_list;
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struct fotg210_itd *last_itd_to_free;
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/* per root hub port */
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unsigned long reset_done[FOTG210_MAX_ROOT_PORTS];
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/* bit vectors (one bit per port)
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* which ports were already suspended at the start of a bus suspend
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*/
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unsigned long bus_suspended;
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/* which ports are edicated to the companion controller */
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unsigned long companion_ports;
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/* which ports are owned by the companion during a bus suspend */
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unsigned long owned_ports;
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/* which ports have the change-suspend feature turned on */
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unsigned long port_c_suspend;
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/* which ports are suspended */
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unsigned long suspended_ports;
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/* which ports have started to resume */
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unsigned long resuming_ports;
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/* per-HC memory pools (could be per-bus, but ...) */
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struct dma_pool *qh_pool; /* qh per active urb */
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struct dma_pool *qtd_pool; /* one or more per qh */
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struct dma_pool *itd_pool; /* itd per iso urb */
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unsigned random_frame;
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unsigned long next_statechange;
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ktime_t last_periodic_enable;
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u32 command;
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/* SILICON QUIRKS */
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unsigned need_io_watchdog:1;
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unsigned fs_i_thresh:1; /* Intel iso scheduling */
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u8 sbrn; /* packed release number */
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/* irq statistics */
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#ifdef FOTG210_STATS
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struct fotg210_stats stats;
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# define INCR(x) ((x)++)
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#else
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# define INCR(x) do {} while (0)
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#endif
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/* silicon clock */
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struct clk *pclk;
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/* debug files */
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struct dentry *debug_dir;
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};
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/* convert between an HCD pointer and the corresponding FOTG210_HCD */
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static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
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{
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return (struct fotg210_hcd *)(hcd->hcd_priv);
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}
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static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
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{
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return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
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}
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/*-------------------------------------------------------------------------*/
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/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
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/* Section 2.2 Host Controller Capability Registers */
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struct fotg210_caps {
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/* these fields are specified as 8 and 16 bit registers,
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* but some hosts can't perform 8 or 16 bit PCI accesses.
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* some hosts treat caplength and hciversion as parts of a 32-bit
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* register, others treat them as two separate registers, this
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* affects the memory map for big endian controllers.
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*/
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u32 hc_capbase;
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#define HC_LENGTH(fotg210, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
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(fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
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#define HC_VERSION(fotg210, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
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(fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
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u32 hcs_params; /* HCSPARAMS - offset 0x4 */
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#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
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u32 hcc_params; /* HCCPARAMS - offset 0x8 */
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#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
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#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
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u8 portroute[8]; /* nibbles for routing - offset 0xC */
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};
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/* Section 2.3 Host Controller Operational Registers */
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struct fotg210_regs {
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/* USBCMD: offset 0x00 */
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u32 command;
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/* EHCI 1.1 addendum */
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/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
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#define CMD_PARK (1<<11) /* enable "park" on async qh */
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#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
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#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
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#define CMD_ASE (1<<5) /* async schedule enable */
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#define CMD_PSE (1<<4) /* periodic schedule enable */
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/* 3:2 is periodic frame list size */
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#define CMD_RESET (1<<1) /* reset HC not bus */
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#define CMD_RUN (1<<0) /* start/stop HC */
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/* USBSTS: offset 0x04 */
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u32 status;
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#define STS_ASS (1<<15) /* Async Schedule Status */
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#define STS_PSS (1<<14) /* Periodic Schedule Status */
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#define STS_RECL (1<<13) /* Reclamation */
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#define STS_HALT (1<<12) /* Not running (any reason) */
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/* some bits reserved */
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/* these STS_* flags are also intr_enable bits (USBINTR) */
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#define STS_IAA (1<<5) /* Interrupted on async advance */
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#define STS_FATAL (1<<4) /* such as some PCI access errors */
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#define STS_FLR (1<<3) /* frame list rolled over */
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#define STS_PCD (1<<2) /* port change detect */
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#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
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#define STS_INT (1<<0) /* "normal" completion (short, ...) */
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/* USBINTR: offset 0x08 */
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u32 intr_enable;
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/* FRINDEX: offset 0x0C */
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u32 frame_index; /* current microframe number */
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/* CTRLDSSEGMENT: offset 0x10 */
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u32 segment; /* address bits 63:32 if needed */
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/* PERIODICLISTBASE: offset 0x14 */
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u32 frame_list; /* points to periodic list */
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/* ASYNCLISTADDR: offset 0x18 */
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u32 async_next; /* address of next async queue head */
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u32 reserved1;
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/* PORTSC: offset 0x20 */
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u32 port_status;
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/* 31:23 reserved */
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#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */
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#define PORT_RESET (1<<8) /* reset port */
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#define PORT_SUSPEND (1<<7) /* suspend port */
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#define PORT_RESUME (1<<6) /* resume it */
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#define PORT_PEC (1<<3) /* port enable change */
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#define PORT_PE (1<<2) /* port enable */
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#define PORT_CSC (1<<1) /* connect status change */
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#define PORT_CONNECT (1<<0) /* device connected */
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#define PORT_RWC_BITS (PORT_CSC | PORT_PEC)
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u32 reserved2[19];
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/* OTGCSR: offet 0x70 */
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u32 otgcsr;
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#define OTGCSR_HOST_SPD_TYP (3 << 22)
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#define OTGCSR_A_BUS_DROP (1 << 5)
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#define OTGCSR_A_BUS_REQ (1 << 4)
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/* OTGISR: offset 0x74 */
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u32 otgisr;
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#define OTGISR_OVC (1 << 10)
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u32 reserved3[15];
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/* GMIR: offset 0xB4 */
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u32 gmir;
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#define GMIR_INT_POLARITY (1 << 3) /*Active High*/
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#define GMIR_MHC_INT (1 << 2)
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#define GMIR_MOTG_INT (1 << 1)
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#define GMIR_MDEV_INT (1 << 0)
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};
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/*-------------------------------------------------------------------------*/
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#define QTD_NEXT(fotg210, dma) cpu_to_hc32(fotg210, (u32)dma)
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/*
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* EHCI Specification 0.95 Section 3.5
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* QTD: describe data transfer components (buffer, direction, ...)
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* See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
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*
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* These are associated only with "QH" (Queue Head) structures,
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* used with control, bulk, and interrupt transfers.
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*/
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struct fotg210_qtd {
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/* first part defined by EHCI spec */
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__hc32 hw_next; /* see EHCI 3.5.1 */
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__hc32 hw_alt_next; /* see EHCI 3.5.2 */
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__hc32 hw_token; /* see EHCI 3.5.3 */
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#define QTD_TOGGLE (1 << 31) /* data toggle */
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#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
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#define QTD_IOC (1 << 15) /* interrupt on complete */
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#define QTD_CERR(tok) (((tok)>>10) & 0x3)
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#define QTD_PID(tok) (((tok)>>8) & 0x3)
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#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
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#define QTD_STS_HALT (1 << 6) /* halted on error */
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#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
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#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
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#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
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#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
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#define QTD_STS_STS (1 << 1) /* split transaction state */
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#define QTD_STS_PING (1 << 0) /* issue PING? */
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#define ACTIVE_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
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#define HALT_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_HALT)
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#define STATUS_BIT(fotg210) cpu_to_hc32(fotg210, QTD_STS_STS)
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__hc32 hw_buf[5]; /* see EHCI 3.5.4 */
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__hc32 hw_buf_hi[5]; /* Appendix B */
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/* the rest is HCD-private */
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dma_addr_t qtd_dma; /* qtd address */
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struct list_head qtd_list; /* sw qtd list */
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struct urb *urb; /* qtd's urb */
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size_t length; /* length of buffer */
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} __aligned(32);
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/* mask NakCnt+T in qh->hw_alt_next */
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#define QTD_MASK(fotg210) cpu_to_hc32(fotg210, ~0x1f)
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#define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
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/*-------------------------------------------------------------------------*/
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/* type tag from {qh,itd,fstn}->hw_next */
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#define Q_NEXT_TYPE(fotg210, dma) ((dma) & cpu_to_hc32(fotg210, 3 << 1))
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/*
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* Now the following defines are not converted using the
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* cpu_to_le32() macro anymore, since we have to support
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* "dynamic" switching between be and le support, so that the driver
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* can be used on one system with SoC EHCI controller using big-endian
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* descriptors as well as a normal little-endian PCI EHCI controller.
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*/
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/* values for that type tag */
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#define Q_TYPE_ITD (0 << 1)
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#define Q_TYPE_QH (1 << 1)
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#define Q_TYPE_SITD (2 << 1)
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#define Q_TYPE_FSTN (3 << 1)
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/* next async queue entry, or pointer to interrupt/periodic QH */
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#define QH_NEXT(fotg210, dma) \
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(cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
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/* for periodic/async schedules and qtd lists, mark end of list */
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#define FOTG210_LIST_END(fotg210) \
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cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
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/*
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* Entries in periodic shadow table are pointers to one of four kinds
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* of data structure. That's dictated by the hardware; a type tag is
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* encoded in the low bits of the hardware's periodic schedule. Use
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* Q_NEXT_TYPE to get the tag.
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*
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* For entries in the async schedule, the type tag always says "qh".
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*/
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union fotg210_shadow {
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struct fotg210_qh *qh; /* Q_TYPE_QH */
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struct fotg210_itd *itd; /* Q_TYPE_ITD */
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struct fotg210_fstn *fstn; /* Q_TYPE_FSTN */
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__hc32 *hw_next; /* (all types) */
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void *ptr;
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};
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/*-------------------------------------------------------------------------*/
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/*
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* EHCI Specification 0.95 Section 3.6
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* QH: describes control/bulk/interrupt endpoints
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* See Fig 3-7 "Queue Head Structure Layout".
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*
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* These appear in both the async and (for interrupt) periodic schedules.
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*/
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/* first part defined by EHCI spec */
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struct fotg210_qh_hw {
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__hc32 hw_next; /* see EHCI 3.6.1 */
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__hc32 hw_info1; /* see EHCI 3.6.2 */
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#define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */
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#define QH_HEAD (1 << 15) /* Head of async reclamation list */
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#define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */
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#define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */
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#define QH_LOW_SPEED (1 << 12)
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#define QH_FULL_SPEED (0 << 12)
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#define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
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__hc32 hw_info2; /* see EHCI 3.6.2 */
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#define QH_SMASK 0x000000ff
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#define QH_CMASK 0x0000ff00
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#define QH_HUBADDR 0x007f0000
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#define QH_HUBPORT 0x3f800000
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#define QH_MULT 0xc0000000
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__hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
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/* qtd overlay (hardware parts of a struct fotg210_qtd) */
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__hc32 hw_qtd_next;
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__hc32 hw_alt_next;
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__hc32 hw_token;
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__hc32 hw_buf[5];
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__hc32 hw_buf_hi[5];
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} __aligned(32);
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struct fotg210_qh {
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struct fotg210_qh_hw *hw; /* Must come first */
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/* the rest is HCD-private */
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dma_addr_t qh_dma; /* address of qh */
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union fotg210_shadow qh_next; /* ptr to qh; or periodic */
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struct list_head qtd_list; /* sw qtd list */
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struct list_head intr_node; /* list of intr QHs */
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struct fotg210_qtd *dummy;
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struct fotg210_qh *unlink_next; /* next on unlink list */
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unsigned unlink_cycle;
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u8 needs_rescan; /* Dequeue during giveback */
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u8 qh_state;
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#define QH_STATE_LINKED 1 /* HC sees this */
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#define QH_STATE_UNLINK 2 /* HC may still see this */
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#define QH_STATE_IDLE 3 /* HC doesn't see this */
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#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */
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#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
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u8 xacterrs; /* XactErr retry counter */
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#define QH_XACTERR_MAX 32 /* XactErr retry limit */
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/* periodic schedule info */
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u8 usecs; /* intr bandwidth */
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u8 gap_uf; /* uframes split/csplit gap */
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u8 c_usecs; /* ... split completion bw */
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u16 tt_usecs; /* tt downstream bandwidth */
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unsigned short period; /* polling interval */
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unsigned short start; /* where polling starts */
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#define NO_FRAME ((unsigned short)~0) /* pick new start */
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struct usb_device *dev; /* access to TT */
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unsigned is_out:1; /* bulk or intr OUT */
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unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
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};
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/*-------------------------------------------------------------------------*/
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/* description of one iso transaction (up to 3 KB data if highspeed) */
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struct fotg210_iso_packet {
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/* These will be copied to iTD when scheduling */
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u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
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__hc32 transaction; /* itd->hw_transaction[i] |= */
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u8 cross; /* buf crosses pages */
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/* for full speed OUT splits */
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u32 buf1;
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};
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/* temporary schedule data for packets from iso urbs (both speeds)
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* each packet is one logical usb transaction to the device (not TT),
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* beginning at stream->next_uframe
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*/
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struct fotg210_iso_sched {
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struct list_head td_list;
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unsigned span;
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struct fotg210_iso_packet packet[];
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};
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/*
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* fotg210_iso_stream - groups all (s)itds for this endpoint.
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* acts like a qh would, if EHCI had them for ISO.
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*/
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struct fotg210_iso_stream {
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/* first field matches fotg210_hq, but is NULL */
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struct fotg210_qh_hw *hw;
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u8 bEndpointAddress;
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u8 highspeed;
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struct list_head td_list; /* queued itds */
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struct list_head free_list; /* list of unused itds */
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struct usb_device *udev;
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struct usb_host_endpoint *ep;
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/* output of (re)scheduling */
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int next_uframe;
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__hc32 splits;
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/* the rest is derived from the endpoint descriptor,
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* trusting urb->interval == f(epdesc->bInterval) and
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* including the extra info for hw_bufp[0..2]
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*/
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u8 usecs, c_usecs;
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u16 interval;
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u16 tt_usecs;
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u16 maxp;
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u16 raw_mask;
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unsigned bandwidth;
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/* This is used to initialize iTD's hw_bufp fields */
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__hc32 buf0;
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__hc32 buf1;
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__hc32 buf2;
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/* this is used to initialize sITD's tt info */
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__hc32 address;
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};
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/*-------------------------------------------------------------------------*/
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/*
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* EHCI Specification 0.95 Section 3.3
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* Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
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*
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* Schedule records for high speed iso xfers
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*/
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struct fotg210_itd {
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/* first part defined by EHCI spec */
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__hc32 hw_next; /* see EHCI 3.3.1 */
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__hc32 hw_transaction[8]; /* see EHCI 3.3.2 */
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#define FOTG210_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
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#define FOTG210_ISOC_BUF_ERR (1<<30) /* Data buffer error */
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#define FOTG210_ISOC_BABBLE (1<<29) /* babble detected */
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#define FOTG210_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
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#define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
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#define FOTG210_ITD_IOC (1 << 15) /* interrupt on complete */
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#define ITD_ACTIVE(fotg210) cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
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__hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
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__hc32 hw_bufp_hi[7]; /* Appendix B */
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/* the rest is HCD-private */
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dma_addr_t itd_dma; /* for this itd */
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union fotg210_shadow itd_next; /* ptr to periodic q entry */
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struct urb *urb;
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struct fotg210_iso_stream *stream; /* endpoint's queue */
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struct list_head itd_list; /* list of stream's itds */
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/* any/all hw_transactions here may be used by that urb */
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unsigned frame; /* where scheduled */
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unsigned pg;
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unsigned index[8]; /* in urb->iso_frame_desc */
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} __aligned(32);
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/*-------------------------------------------------------------------------*/
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/*
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* EHCI Specification 0.96 Section 3.7
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* Periodic Frame Span Traversal Node (FSTN)
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*
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* Manages split interrupt transactions (using TT) that span frame boundaries
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* into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
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* makes the HC jump (back) to a QH to scan for fs/ls QH completions until
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* it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
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*/
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struct fotg210_fstn {
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__hc32 hw_next; /* any periodic q entry */
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__hc32 hw_prev; /* qh or FOTG210_LIST_END */
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/* the rest is HCD-private */
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dma_addr_t fstn_dma;
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union fotg210_shadow fstn_next; /* ptr to periodic q entry */
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} __aligned(32);
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/*-------------------------------------------------------------------------*/
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/* Prepare the PORTSC wakeup flags during controller suspend/resume */
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#define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
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fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup)
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#define fotg210_prepare_ports_for_controller_resume(fotg210) \
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fotg210_adjust_port_wakeup_flags(fotg210, false, false)
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/*-------------------------------------------------------------------------*/
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/*
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* Some EHCI controllers have a Transaction Translator built into the
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* root hub. This is a non-standard feature. Each controller will need
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* to add code to the following inline functions, and call them as
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* needed (mostly in root hub code).
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*/
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static inline unsigned int
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fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
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{
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return (readl(&fotg210->regs->otgcsr)
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& OTGCSR_HOST_SPD_TYP) >> 22;
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}
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/* Returns the speed of a device attached to a port on the root hub. */
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static inline unsigned int
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fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
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{
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switch (fotg210_get_speed(fotg210, portsc)) {
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case 0:
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return 0;
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case 1:
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return USB_PORT_STAT_LOW_SPEED;
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case 2:
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default:
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return USB_PORT_STAT_HIGH_SPEED;
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}
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}
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/*-------------------------------------------------------------------------*/
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#define fotg210_has_fsl_portno_bug(e) (0)
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/*
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* While most USB host controllers implement their registers in
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* little-endian format, a minority (celleb companion chip) implement
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* them in big endian format.
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*
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* This attempts to support either format at compile time without a
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* runtime penalty, or both formats with the additional overhead
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* of checking a flag bit.
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*
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*/
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#define fotg210_big_endian_mmio(e) 0
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#define fotg210_big_endian_capbase(e) 0
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static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
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__u32 __iomem *regs)
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{
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return readl(regs);
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}
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static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
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const unsigned int val, __u32 __iomem *regs)
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{
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writel(val, regs);
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}
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/* cpu to fotg210 */
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static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
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{
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return cpu_to_le32(x);
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}
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/* fotg210 to cpu */
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static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
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{
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return le32_to_cpu(x);
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}
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static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
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const __hc32 *x)
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{
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return le32_to_cpup(x);
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}
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/*-------------------------------------------------------------------------*/
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static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
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{
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return fotg210_readl(fotg210, &fotg210->regs->frame_index);
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}
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/*-------------------------------------------------------------------------*/
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#endif /* __LINUX_FOTG210_H */
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