// SPDX-License-Identifier: GPL-2.0
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#include <linux/kernel.h>
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#include <linux/sizes.h>
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#include "ddk750_reg.h"
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#include "ddk750_chip.h"
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#include "ddk750_power.h"
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#define MHz(x) ((x) * 1000000)
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static enum logical_chip_type chip;
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enum logical_chip_type sm750_get_chip_type(void)
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{
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return chip;
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}
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void sm750_set_chip_type(unsigned short dev_id, u8 rev_id)
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{
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if (dev_id == 0x718) {
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chip = SM718;
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} else if (dev_id == 0x750) {
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chip = SM750;
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/* SM750 and SM750LE are different in their revision ID only. */
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if (rev_id == SM750LE_REVISION_ID) {
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chip = SM750LE;
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pr_info("found sm750le\n");
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}
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} else {
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chip = SM_UNKNOWN;
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}
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}
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static unsigned int get_mxclk_freq(void)
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{
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unsigned int pll_reg;
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unsigned int M, N, OD, POD;
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if (sm750_get_chip_type() == SM750LE)
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return MHz(130);
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pll_reg = peek32(MXCLK_PLL_CTRL);
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M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT;
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N = (pll_reg & PLL_CTRL_N_MASK) >> PLL_CTRL_N_SHIFT;
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OD = (pll_reg & PLL_CTRL_OD_MASK) >> PLL_CTRL_OD_SHIFT;
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POD = (pll_reg & PLL_CTRL_POD_MASK) >> PLL_CTRL_POD_SHIFT;
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return DEFAULT_INPUT_CLOCK * M / N / BIT(OD) / BIT(POD);
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}
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/*
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* This function set up the main chip clock.
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*
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* Input: Frequency to be set.
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*/
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static void set_chip_clock(unsigned int frequency)
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{
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struct pll_value pll;
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/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
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if (sm750_get_chip_type() == SM750LE)
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return;
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if (frequency) {
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/*
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* Set up PLL structure to hold the value to be set in clocks.
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*/
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pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
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pll.clock_type = MXCLK_PLL;
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/*
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* Call sm750_calc_pll_value() to fill the other fields
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* of the PLL structure. Sometimes, the chip cannot set
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* up the exact clock required by the User.
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* Return value of sm750_calc_pll_value gives the actual
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* possible clock.
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*/
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sm750_calc_pll_value(frequency, &pll);
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/* Master Clock Control: MXCLK_PLL */
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poke32(MXCLK_PLL_CTRL, sm750_format_pll_reg(&pll));
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}
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}
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static void set_memory_clock(unsigned int frequency)
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{
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unsigned int reg, divisor;
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/*
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* Cheok_0509: For SM750LE, the memory clock is fixed.
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* Nothing to set.
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*/
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if (sm750_get_chip_type() == SM750LE)
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return;
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if (frequency) {
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/*
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* Set the frequency to the maximum frequency
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* that the DDR Memory can take which is 336MHz.
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*/
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if (frequency > MHz(336))
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frequency = MHz(336);
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/* Calculate the divisor */
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divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);
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/* Set the corresponding divisor in the register. */
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reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
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switch (divisor) {
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default:
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case 1:
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reg |= CURRENT_GATE_M2XCLK_DIV_1;
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break;
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case 2:
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reg |= CURRENT_GATE_M2XCLK_DIV_2;
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break;
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case 3:
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reg |= CURRENT_GATE_M2XCLK_DIV_3;
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break;
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case 4:
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reg |= CURRENT_GATE_M2XCLK_DIV_4;
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break;
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}
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sm750_set_current_gate(reg);
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}
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}
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/*
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* This function set up the master clock (MCLK).
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*
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* Input: Frequency to be set.
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*
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* NOTE:
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* The maximum frequency the engine can run is 168MHz.
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*/
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static void set_master_clock(unsigned int frequency)
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{
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unsigned int reg, divisor;
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/*
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* Cheok_0509: For SM750LE, the memory clock is fixed.
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* Nothing to set.
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*/
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if (sm750_get_chip_type() == SM750LE)
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return;
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if (frequency) {
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/*
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* Set the frequency to the maximum frequency
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* that the SM750 engine can run, which is about 190 MHz.
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*/
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if (frequency > MHz(190))
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frequency = MHz(190);
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/* Calculate the divisor */
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divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);
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/* Set the corresponding divisor in the register. */
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reg = peek32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK;
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switch (divisor) {
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default:
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case 3:
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reg |= CURRENT_GATE_MCLK_DIV_3;
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break;
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case 4:
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reg |= CURRENT_GATE_MCLK_DIV_4;
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break;
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case 6:
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reg |= CURRENT_GATE_MCLK_DIV_6;
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break;
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case 8:
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reg |= CURRENT_GATE_MCLK_DIV_8;
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break;
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}
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sm750_set_current_gate(reg);
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}
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}
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unsigned int ddk750_get_vm_size(void)
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{
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unsigned int reg;
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unsigned int data;
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/* sm750le only use 64 mb memory*/
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if (sm750_get_chip_type() == SM750LE)
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return SZ_64M;
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/* for 750,always use power mode0*/
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reg = peek32(MODE0_GATE);
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reg |= MODE0_GATE_GPIO;
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poke32(MODE0_GATE, reg);
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/* get frame buffer size from GPIO */
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reg = peek32(MISC_CTRL) & MISC_CTRL_LOCALMEM_SIZE_MASK;
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switch (reg) {
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case MISC_CTRL_LOCALMEM_SIZE_8M:
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data = SZ_8M; break; /* 8 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_16M:
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data = SZ_16M; break; /* 16 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_32M:
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data = SZ_32M; break; /* 32 Mega byte */
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case MISC_CTRL_LOCALMEM_SIZE_64M:
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data = SZ_64M; break; /* 64 Mega byte */
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default:
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data = 0;
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break;
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}
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return data;
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}
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int ddk750_init_hw(struct initchip_param *p_init_param)
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{
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unsigned int reg;
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if (p_init_param->power_mode != 0)
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p_init_param->power_mode = 0;
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sm750_set_power_mode(p_init_param->power_mode);
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/* Enable display power gate & LOCALMEM power gate*/
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reg = peek32(CURRENT_GATE);
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reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
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sm750_set_current_gate(reg);
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if (sm750_get_chip_type() != SM750LE) {
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/* set panel pll and graphic mode via mmio_88 */
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reg = peek32(VGA_CONFIGURATION);
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reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE);
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poke32(VGA_CONFIGURATION, reg);
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} else {
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#if defined(__i386__) || defined(__x86_64__)
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/* set graphic mode via IO method */
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outb_p(0x88, 0x3d4);
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outb_p(0x06, 0x3d5);
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#endif
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}
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/* Set the Main Chip Clock */
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set_chip_clock(MHz((unsigned int)p_init_param->chip_clock));
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/* Set up memory clock. */
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set_memory_clock(MHz(p_init_param->mem_clock));
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/* Set up master clock */
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set_master_clock(MHz(p_init_param->master_clock));
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/*
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* Reset the memory controller.
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* If the memory controller is not reset in SM750,
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* the system might hang when sw accesses the memory.
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* The memory should be resetted after changing the MXCLK.
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*/
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if (p_init_param->reset_memory == 1) {
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reg = peek32(MISC_CTRL);
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reg &= ~MISC_CTRL_LOCALMEM_RESET;
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poke32(MISC_CTRL, reg);
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reg |= MISC_CTRL_LOCALMEM_RESET;
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poke32(MISC_CTRL, reg);
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}
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if (p_init_param->set_all_eng_off == 1) {
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sm750_enable_2d_engine(0);
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/* Disable Overlay, if a former application left it on */
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reg = peek32(VIDEO_DISPLAY_CTRL);
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reg &= ~DISPLAY_CTRL_PLANE;
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poke32(VIDEO_DISPLAY_CTRL, reg);
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/* Disable video alpha, if a former application left it on */
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reg = peek32(VIDEO_ALPHA_DISPLAY_CTRL);
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reg &= ~DISPLAY_CTRL_PLANE;
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poke32(VIDEO_ALPHA_DISPLAY_CTRL, reg);
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/* Disable alpha plane, if a former application left it on */
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reg = peek32(ALPHA_DISPLAY_CTRL);
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reg &= ~DISPLAY_CTRL_PLANE;
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poke32(ALPHA_DISPLAY_CTRL, reg);
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/* Disable DMA Channel, if a former application left it on */
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reg = peek32(DMA_ABORT_INTERRUPT);
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reg |= DMA_ABORT_INTERRUPT_ABORT_1;
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poke32(DMA_ABORT_INTERRUPT, reg);
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/* Disable DMA Power, if a former application left it on */
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sm750_enable_dma(0);
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}
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/* We can add more initialization as needed. */
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return 0;
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}
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/*
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* monk liu @ 4/6/2011:
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* re-write the calculatePLL function of ddk750.
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* the original version function does not use
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* some mathematics tricks and shortcut
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* when it doing the calculation of the best N,M,D combination
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* I think this version gives a little upgrade in speed
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*
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* 750 pll clock formular:
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* Request Clock = (Input Clock * M )/(N * X)
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*
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* Input Clock = 14318181 hz
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* X = 2 power D
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* D ={0,1,2,3,4,5,6}
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* M = {1,...,255}
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* N = {2,...,15}
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*/
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unsigned int sm750_calc_pll_value(unsigned int request_orig,
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struct pll_value *pll)
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{
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/*
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* as sm750 register definition,
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* N located in 2,15 and M located in 1,255
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*/
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int N, M, X, d;
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int mini_diff;
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unsigned int RN, quo, rem, fl_quo;
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unsigned int input, request;
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unsigned int tmp_clock, ret;
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const int max_OD = 3;
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int max_d = 6;
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if (sm750_get_chip_type() == SM750LE) {
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/*
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* SM750LE don't have
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* programmable PLL and M/N values to work on.
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* Just return the requested clock.
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*/
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return request_orig;
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}
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ret = 0;
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mini_diff = ~0;
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request = request_orig / 1000;
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input = pll->input_freq / 1000;
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/*
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* for MXCLK register,
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* no POD provided, so need be treated differently
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*/
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if (pll->clock_type == MXCLK_PLL)
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max_d = 3;
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for (N = 15; N > 1; N--) {
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/*
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* RN will not exceed maximum long
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* if @request <= 285 MHZ (for 32bit cpu)
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*/
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RN = N * request;
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quo = RN / input;
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rem = RN % input;/* rem always small than 14318181 */
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fl_quo = rem * 10000 / input;
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for (d = max_d; d >= 0; d--) {
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X = BIT(d);
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M = quo * X;
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M += fl_quo * X / 10000;
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/* round step */
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M += (fl_quo * X % 10000) > 5000 ? 1 : 0;
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if (M < 256 && M > 0) {
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unsigned int diff;
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tmp_clock = pll->input_freq * M / N / X;
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diff = abs(tmp_clock - request_orig);
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if (diff < mini_diff) {
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pll->M = M;
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pll->N = N;
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pll->POD = 0;
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if (d > max_OD)
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pll->POD = d - max_OD;
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pll->OD = d - pll->POD;
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mini_diff = diff;
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ret = tmp_clock;
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}
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}
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}
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}
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return ret;
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}
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unsigned int sm750_format_pll_reg(struct pll_value *p_PLL)
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{
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#ifndef VALIDATION_CHIP
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unsigned int POD = p_PLL->POD;
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#endif
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unsigned int OD = p_PLL->OD;
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unsigned int M = p_PLL->M;
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unsigned int N = p_PLL->N;
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/*
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* Note that all PLL's have the same format. Here, we just use
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* Panel PLL parameter to work out the bit fields in the
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* register. On returning a 32 bit number, the value can be
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* applied to any PLL in the calling function.
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*/
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return PLL_CTRL_POWER |
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#ifndef VALIDATION_CHIP
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((POD << PLL_CTRL_POD_SHIFT) & PLL_CTRL_POD_MASK) |
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#endif
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((OD << PLL_CTRL_OD_SHIFT) & PLL_CTRL_OD_MASK) |
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((N << PLL_CTRL_N_SHIFT) & PLL_CTRL_N_MASK) |
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((M << PLL_CTRL_M_SHIFT) & PLL_CTRL_M_MASK);
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}
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