/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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*/
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#ifndef __MESON_VDEC_HEVC_REGS_H_
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#define __MESON_VDEC_HEVC_REGS_H_
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#define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
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#define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
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#define HEVC_ASSIST_MBOX1_MASK 0xc1d8
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#define HEVC_ASSIST_SCRATCH_0 0xc300
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#define HEVC_ASSIST_SCRATCH_1 0xc304
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#define HEVC_ASSIST_SCRATCH_2 0xc308
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#define HEVC_ASSIST_SCRATCH_3 0xc30c
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#define HEVC_ASSIST_SCRATCH_4 0xc310
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#define HEVC_ASSIST_SCRATCH_5 0xc314
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#define HEVC_ASSIST_SCRATCH_6 0xc318
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#define HEVC_ASSIST_SCRATCH_7 0xc31c
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#define HEVC_ASSIST_SCRATCH_8 0xc320
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#define HEVC_ASSIST_SCRATCH_9 0xc324
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#define HEVC_ASSIST_SCRATCH_A 0xc328
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#define HEVC_ASSIST_SCRATCH_B 0xc32c
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#define HEVC_ASSIST_SCRATCH_C 0xc330
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#define HEVC_ASSIST_SCRATCH_D 0xc334
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#define HEVC_ASSIST_SCRATCH_E 0xc338
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#define HEVC_ASSIST_SCRATCH_F 0xc33c
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#define HEVC_ASSIST_SCRATCH_G 0xc340
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#define HEVC_ASSIST_SCRATCH_H 0xc344
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#define HEVC_ASSIST_SCRATCH_I 0xc348
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#define HEVC_ASSIST_SCRATCH_J 0xc34c
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#define HEVC_ASSIST_SCRATCH_K 0xc350
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#define HEVC_ASSIST_SCRATCH_L 0xc354
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#define HEVC_ASSIST_SCRATCH_M 0xc358
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#define HEVC_ASSIST_SCRATCH_N 0xc35c
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#define HEVC_PARSER_VERSION 0xc400
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#define HEVC_STREAM_CONTROL 0xc404
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#define HEVC_STREAM_START_ADDR 0xc408
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#define HEVC_STREAM_END_ADDR 0xc40c
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#define HEVC_STREAM_WR_PTR 0xc410
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#define HEVC_STREAM_RD_PTR 0xc414
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#define HEVC_STREAM_LEVEL 0xc418
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#define HEVC_STREAM_FIFO_CTL 0xc41c
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#define HEVC_SHIFT_CONTROL 0xc420
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#define HEVC_SHIFT_STARTCODE 0xc424
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#define HEVC_SHIFT_EMULATECODE 0xc428
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#define HEVC_SHIFT_STATUS 0xc42c
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#define HEVC_SHIFTED_DATA 0xc430
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#define HEVC_SHIFT_BYTE_COUNT 0xc434
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#define HEVC_SHIFT_COMMAND 0xc438
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#define HEVC_ELEMENT_RESULT 0xc43c
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#define HEVC_CABAC_CONTROL 0xc440
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#define HEVC_PARSER_SLICE_INFO 0xc444
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#define HEVC_PARSER_CMD_WRITE 0xc448
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#define HEVC_PARSER_CORE_CONTROL 0xc44c
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#define HEVC_PARSER_CMD_FETCH 0xc450
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#define HEVC_PARSER_CMD_STATUS 0xc454
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#define HEVC_PARSER_LCU_INFO 0xc458
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#define HEVC_PARSER_HEADER_INFO 0xc45c
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#define HEVC_PARSER_INT_CONTROL 0xc480
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#define HEVC_PARSER_INT_STATUS 0xc484
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#define HEVC_PARSER_IF_CONTROL 0xc488
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#define HEVC_PARSER_PICTURE_SIZE 0xc48c
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#define HEVC_PARSER_LCU_START 0xc490
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#define HEVC_PARSER_HEADER_INFO2 0xc494
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#define HEVC_PARSER_QUANT_READ 0xc498
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#define HEVC_PARSER_RESERVED_27 0xc49c
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#define HEVC_PARSER_CMD_SKIP_0 0xc4a0
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#define HEVC_PARSER_CMD_SKIP_1 0xc4a4
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#define HEVC_PARSER_CMD_SKIP_2 0xc4a8
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#define HEVC_SAO_IF_STATUS 0xc4c0
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#define HEVC_SAO_IF_DATA_Y 0xc4c4
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#define HEVC_SAO_IF_DATA_U 0xc4c8
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#define HEVC_SAO_IF_DATA_V 0xc4cc
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#define HEVC_STREAM_SWAP_ADDR 0xc4d0
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#define HEVC_STREAM_SWAP_CTRL 0xc4d4
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#define HEVC_IQIT_IF_WAIT_CNT 0xc4d8
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#define HEVC_MPRED_IF_WAIT_CNT 0xc4dc
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#define HEVC_SAO_IF_WAIT_CNT 0xc4e0
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#define HEVC_MPRED_VERSION 0xc800
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#define HEVC_MPRED_CTRL0 0xc804
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#define MPRED_CTRL0_NEW_PIC BIT(2)
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#define MPRED_CTRL0_NEW_TILE BIT(3)
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#define MPRED_CTRL0_NEW_SLI_SEG BIT(4)
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#define MPRED_CTRL0_TMVP BIT(5)
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#define MPRED_CTRL0_LDC BIT(6)
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#define MPRED_CTRL0_COL_FROM_L0 BIT(7)
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#define MPRED_CTRL0_ABOVE_EN BIT(9)
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#define MPRED_CTRL0_MV_WR_EN BIT(10)
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#define MPRED_CTRL0_MV_RD_EN BIT(11)
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#define MPRED_CTRL0_BUF_LINEAR BIT(13)
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#define HEVC_MPRED_CTRL1 0xc808
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#define HEVC_MPRED_INT_EN 0xc80c
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#define HEVC_MPRED_INT_STATUS 0xc810
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#define HEVC_MPRED_PIC_SIZE 0xc814
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#define HEVC_MPRED_PIC_SIZE_LCU 0xc818
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#define HEVC_MPRED_TILE_START 0xc81c
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#define HEVC_MPRED_TILE_SIZE_LCU 0xc820
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#define HEVC_MPRED_REF_NUM 0xc824
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#define HEVC_MPRED_REF_EN_L0 0xc830
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#define HEVC_MPRED_REF_EN_L1 0xc834
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#define HEVC_MPRED_COLREF_EN_L0 0xc838
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#define HEVC_MPRED_COLREF_EN_L1 0xc83c
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#define HEVC_MPRED_AXI_WCTRL 0xc840
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#define HEVC_MPRED_AXI_RCTRL 0xc844
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#define HEVC_MPRED_ABV_START_ADDR 0xc848
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#define HEVC_MPRED_MV_WR_START_ADDR 0xc84c
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#define HEVC_MPRED_MV_RD_START_ADDR 0xc850
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#define HEVC_MPRED_MV_WPTR 0xc854
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#define HEVC_MPRED_MV_RPTR 0xc858
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#define HEVC_MPRED_MV_WR_ROW_JUMP 0xc85c
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#define HEVC_MPRED_MV_RD_ROW_JUMP 0xc860
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#define HEVC_MPRED_CURR_LCU 0xc864
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#define HEVC_MPRED_ABV_WPTR 0xc868
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#define HEVC_MPRED_ABV_RPTR 0xc86c
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#define HEVC_MPRED_CTRL2 0xc870
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#define HEVC_MPRED_CTRL3 0xc874
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#define HEVC_MPRED_L0_REF00_POC 0xc880
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#define HEVC_MPRED_L1_REF00_POC 0xc8c0
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#define HEVC_MPRED_CTRL4 0xc930
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#define HEVC_MPRED_CUR_POC 0xc980
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#define HEVC_MPRED_COL_POC 0xc984
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#define HEVC_MPRED_MV_RD_END_ADDR 0xc988
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#define HEVC_MSP 0xcc00
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#define HEVC_MPSR 0xcc04
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#define HEVC_MCPU_INTR_MSK 0xcc10
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#define HEVC_MCPU_INTR_REQ 0xcc14
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#define HEVC_CPSR 0xcc84
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#define HEVC_IMEM_DMA_CTRL 0xcd00
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#define HEVC_IMEM_DMA_ADR 0xcd04
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#define HEVC_IMEM_DMA_COUNT 0xcd08
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#define HEVCD_IPP_TOP_CNTL 0xd000
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#define HEVCD_IPP_LINEBUFF_BASE 0xd024
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#define HEVCD_IPP_AXIIF_CONFIG 0xd02c
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#define VP9D_MPP_REF_SCALE_ENBL 0xd104
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#define VP9D_MPP_REFINFO_TBL_ACCCONFIG 0xd108
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#define VP9D_MPP_REFINFO_DATA 0xd10c
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#define HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR 0xd180
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#define HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR 0xd184
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#define HEVCD_MPP_ANC2AXI_TBL_DATA 0xd190
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#define HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR 0xd300
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#define HEVCD_MPP_ANC_CANVAS_DATA_ADDR 0xd304
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#define HEVCD_MPP_DECOMP_CTL1 0xd308
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#define HEVCD_MPP_DECOMP_CTL2 0xd30c
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#define HEVCD_MCRCC_CTL1 0xd3c0
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#define HEVCD_MCRCC_CTL2 0xd3c4
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#define HEVCD_MCRCC_CTL3 0xd3c8
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#define HEVC_DBLK_CFG0 0xd400
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#define HEVC_DBLK_CFG1 0xd404
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#define HEVC_DBLK_CFG2 0xd408
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#define HEVC_DBLK_CFG3 0xd40c
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#define HEVC_DBLK_CFG4 0xd410
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#define HEVC_DBLK_CFG5 0xd414
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#define HEVC_DBLK_CFG6 0xd418
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#define HEVC_DBLK_CFG7 0xd41c
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#define HEVC_DBLK_CFG8 0xd420
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#define HEVC_DBLK_CFG9 0xd424
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#define HEVC_DBLK_CFGA 0xd428
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#define HEVC_DBLK_STS0 0xd42c
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#define HEVC_DBLK_CFGB 0xd42c
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#define HEVC_DBLK_STS1 0xd430
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#define HEVC_DBLK_CFGE 0xd438
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#define HEVC_SAO_VERSION 0xd800
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#define HEVC_SAO_CTRL0 0xd804
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#define HEVC_SAO_CTRL1 0xd808
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#define HEVC_SAO_PIC_SIZE 0xd814
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#define HEVC_SAO_PIC_SIZE_LCU 0xd818
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#define HEVC_SAO_TILE_START 0xd81c
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#define HEVC_SAO_TILE_SIZE_LCU 0xd820
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#define HEVC_SAO_Y_START_ADDR 0xd82c
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#define HEVC_SAO_Y_LENGTH 0xd830
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#define HEVC_SAO_C_START_ADDR 0xd834
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#define HEVC_SAO_C_LENGTH 0xd838
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#define HEVC_SAO_Y_WPTR 0xd83c
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#define HEVC_SAO_C_WPTR 0xd840
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#define HEVC_SAO_ABV_START_ADDR 0xd844
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#define HEVC_SAO_VB_WR_START_ADDR 0xd848
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#define HEVC_SAO_VB_RD_START_ADDR 0xd84c
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#define HEVC_SAO_ABV_WPTR 0xd850
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#define HEVC_SAO_ABV_RPTR 0xd854
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#define HEVC_SAO_VB_WPTR 0xd858
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#define HEVC_SAO_VB_RPTR 0xd85c
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#define HEVC_SAO_CTRL2 0xd880
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#define HEVC_SAO_CTRL3 0xd884
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#define HEVC_SAO_CTRL4 0xd888
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#define HEVC_SAO_CTRL5 0xd88c
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#define HEVC_SAO_CTRL6 0xd890
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#define HEVC_SAO_CTRL7 0xd894
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#define HEVC_CM_BODY_START_ADDR 0xd898
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#define HEVC_CM_BODY_LENGTH 0xd89c
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#define HEVC_CM_HEADER_START_ADDR 0xd8a0
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#define HEVC_CM_HEADER_LENGTH 0xd8a4
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#define HEVC_CM_HEADER_OFFSET 0xd8ac
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#define HEVC_SAO_MMU_VH0_ADDR 0xd8e8
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#define HEVC_SAO_MMU_VH1_ADDR 0xd8ec
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#define HEVC_IQIT_CLK_RST_CTRL 0xdc00
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#define HEVC_IQIT_SCALELUT_WR_ADDR 0xdc08
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#define HEVC_IQIT_SCALELUT_RD_ADDR 0xdc0c
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#define HEVC_IQIT_SCALELUT_DATA 0xdc10
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#define HEVC_PSCALE_CTRL 0xe444
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#endif
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