/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2018 Intel Corporation */
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#ifndef __IPU3_CSS_FW_H
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#define __IPU3_CSS_FW_H
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/******************* Firmware file definitions *******************/
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#define IMGU_FW_NAME "intel/ipu3-fw.bin"
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typedef u32 imgu_fw_ptr;
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enum imgu_fw_type {
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IMGU_FW_SP_FIRMWARE, /* Firmware for the SP */
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IMGU_FW_SP1_FIRMWARE, /* Firmware for the SP1 */
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IMGU_FW_ISP_FIRMWARE, /* Firmware for the ISP */
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IMGU_FW_BOOTLOADER_FIRMWARE, /* Firmware for the BootLoader */
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IMGU_FW_ACC_FIRMWARE /* Firmware for accelerations */
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};
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enum imgu_fw_acc_type {
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IMGU_FW_ACC_NONE, /* Normal binary */
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IMGU_FW_ACC_OUTPUT, /* Accelerator stage on output frame */
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IMGU_FW_ACC_VIEWFINDER, /* Accelerator stage on viewfinder frame */
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IMGU_FW_ACC_STANDALONE, /* Stand-alone acceleration */
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};
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struct imgu_fw_isp_parameter {
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u32 offset; /* Offset in isp_<mem> config, params, etc. */
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u32 size; /* Disabled if 0 */
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};
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struct imgu_fw_param_memory_offsets {
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struct {
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struct imgu_fw_isp_parameter lin; /* lin_vmem_params */
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struct imgu_fw_isp_parameter tnr3; /* tnr3_vmem_params */
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struct imgu_fw_isp_parameter xnr3; /* xnr3_vmem_params */
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} vmem;
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struct {
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struct imgu_fw_isp_parameter tnr;
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struct imgu_fw_isp_parameter tnr3; /* tnr3_params */
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struct imgu_fw_isp_parameter xnr3; /* xnr3_params */
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struct imgu_fw_isp_parameter plane_io_config; /* 192 bytes */
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struct imgu_fw_isp_parameter rgbir; /* rgbir_params */
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} dmem;
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};
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struct imgu_fw_config_memory_offsets {
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struct {
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struct imgu_fw_isp_parameter iterator;
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struct imgu_fw_isp_parameter dvs;
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struct imgu_fw_isp_parameter output;
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struct imgu_fw_isp_parameter raw;
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struct imgu_fw_isp_parameter input_yuv;
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struct imgu_fw_isp_parameter tnr;
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struct imgu_fw_isp_parameter tnr3;
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struct imgu_fw_isp_parameter ref;
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} dmem;
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};
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struct imgu_fw_state_memory_offsets {
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struct {
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struct imgu_fw_isp_parameter tnr;
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struct imgu_fw_isp_parameter tnr3;
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struct imgu_fw_isp_parameter ref;
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} dmem;
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};
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union imgu_fw_all_memory_offsets {
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struct {
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u64 imgu_fw_mem_offsets[3]; /* params, config, state */
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} offsets;
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struct {
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u64 ptr;
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} array[IMGU_ABI_PARAM_CLASS_NUM];
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};
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struct imgu_fw_binary_xinfo {
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/* Part that is of interest to the SP. */
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struct imgu_abi_binary_info sp;
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/* Rest of the binary info, only interesting to the host. */
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u32 type; /* enum imgu_fw_acc_type */
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u32 num_output_formats __aligned(8);
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u32 output_formats[IMGU_ABI_FRAME_FORMAT_NUM]; /* enum frame_format */
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/* number of supported vf formats */
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u32 num_vf_formats __aligned(8);
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/* types of supported vf formats */
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u32 vf_formats[IMGU_ABI_FRAME_FORMAT_NUM]; /* enum frame_format */
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u8 num_output_pins;
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imgu_fw_ptr xmem_addr;
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u64 imgu_fw_blob_descr_ptr __aligned(8);
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u32 blob_index __aligned(8);
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union imgu_fw_all_memory_offsets mem_offsets __aligned(8);
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struct imgu_fw_binary_xinfo *next __aligned(8);
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};
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struct imgu_fw_sp_info {
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u32 init_dmem_data; /* data sect config, stored to dmem */
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u32 per_frame_data; /* Per frame data, stored to dmem */
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u32 group; /* Per pipeline data, loaded by dma */
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u32 output; /* SP output data, loaded by dmem */
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u32 host_sp_queue; /* Host <-> SP queues */
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u32 host_sp_com; /* Host <-> SP commands */
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u32 isp_started; /* P'ed from sensor thread, csim only */
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u32 sw_state; /* Polled from css, enum imgu_abi_sp_swstate */
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u32 host_sp_queues_initialized; /* Polled from the SP */
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u32 sleep_mode; /* different mode to halt SP */
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u32 invalidate_tlb; /* inform SP to invalidate mmu TLB */
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u32 debug_buffer_ddr_address; /* the addr of DDR debug queue */
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/* input system perf count array */
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u32 perf_counter_input_system_error;
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u32 threads_stack; /* sp thread's stack pointers */
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u32 threads_stack_size; /* sp thread's stack sizes */
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u32 curr_binary_id; /* current binary id */
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u32 raw_copy_line_count; /* raw copy line counter */
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u32 ddr_parameter_address; /* acc param ddrptr, sp dmem */
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u32 ddr_parameter_size; /* acc param size, sp dmem */
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/* Entry functions */
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u32 sp_entry; /* The SP entry function */
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u32 tagger_frames_addr; /* Base address of tagger state */
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};
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struct imgu_fw_bl_info {
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u32 num_dma_cmds; /* Number of cmds sent by CSS */
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u32 dma_cmd_list; /* Dma command list sent by CSS */
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u32 sw_state; /* Polled from css, enum imgu_abi_bl_swstate */
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/* Entry functions */
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u32 bl_entry; /* The SP entry function */
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};
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struct imgu_fw_acc_info {
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u32 per_frame_data; /* Dummy for now */
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};
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union imgu_fw_union {
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struct imgu_fw_binary_xinfo isp; /* ISP info */
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struct imgu_fw_sp_info sp; /* SP info */
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struct imgu_fw_sp_info sp1; /* SP1 info */
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struct imgu_fw_bl_info bl; /* Bootloader info */
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struct imgu_fw_acc_info acc; /* Accelerator info */
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};
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struct imgu_fw_info {
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size_t header_size; /* size of fw header */
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u32 type __aligned(8); /* enum imgu_fw_type */
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union imgu_fw_union info; /* Binary info */
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struct imgu_abi_blob_info blob; /* Blob info */
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/* Dynamic part */
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u64 next;
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u32 loaded __aligned(8); /* Firmware has been loaded */
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const u64 isp_code __aligned(8); /* ISP pointer to code */
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/* Firmware handle between user space and kernel */
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u32 handle __aligned(8);
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/* Sections to copy from/to ISP */
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struct imgu_abi_isp_param_segments mem_initializers;
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/* Initializer for local ISP memories */
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};
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struct imgu_fw_bi_file_h {
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char version[64]; /* branch tag + week day + time */
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int binary_nr; /* Number of binaries */
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unsigned int h_size; /* sizeof(struct imgu_fw_bi_file_h) */
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};
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struct imgu_fw_header {
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struct imgu_fw_bi_file_h file_header;
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struct imgu_fw_info binary_header[]; /* binary_nr items */
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};
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/******************* Firmware functions *******************/
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int imgu_css_fw_init(struct imgu_css *css);
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void imgu_css_fw_cleanup(struct imgu_css *css);
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unsigned int imgu_css_fw_obgrid_size(const struct imgu_fw_info *bi);
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void *imgu_css_fw_pipeline_params(struct imgu_css *css, unsigned int pipe,
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enum imgu_abi_param_class cls,
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enum imgu_abi_memories mem,
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struct imgu_fw_isp_parameter *par,
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size_t par_size, void *binary_params);
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#endif
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