// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip Generic Register Files setup
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*
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* Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
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*/
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#include <linux/bitfield.h>
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#include <linux/err.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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struct rockchip_grf;
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struct rockchip_grf_funcs {
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int (*reset)(struct rockchip_grf *grf);
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};
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struct rockchip_grf {
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struct regmap *regmap;
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const struct rockchip_grf_funcs *funcs;
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};
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static int rockchip_edp_phy_grf_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rockchip_grf *grf;
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int ret;
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grf = devm_kzalloc(dev, sizeof(*grf), GFP_KERNEL);
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if (!grf)
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return -ENOMEM;
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grf->funcs = of_device_get_match_data(dev);
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if (!grf->funcs)
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return -ENODEV;
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grf->regmap = syscon_node_to_regmap(dev->of_node);
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if (IS_ERR(grf->regmap)) {
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ret = PTR_ERR(grf->regmap);
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dev_err(dev, "failed to get grf: %d\n", ret);
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return ret;
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}
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ret = grf->funcs->reset(grf);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, grf);
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return 0;
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}
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static int __maybe_unused rockchip_edp_phy_grf_resume(struct device *dev)
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{
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struct rockchip_grf *grf = dev_get_drvdata(dev);
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return grf->funcs->reset(grf);
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}
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static const struct dev_pm_ops rockchip_edp_phy_grf_pm_ops = {
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SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rockchip_edp_phy_grf_resume)
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};
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static int rk3568_edp_phy_grf_reset(struct rockchip_grf *grf)
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{
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u32 status;
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int ret;
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ret = regmap_read(grf->regmap, 0x0030, &status);
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if (ret < 0)
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return ret;
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if (!FIELD_GET(0x1, status)) {
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regmap_write(grf->regmap, 0x0028, 0x00070007);
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regmap_write(grf->regmap, 0x0000, 0x0ff10ff1);
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}
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return 0;
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}
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static const struct rockchip_grf_funcs rk3568_edp_phy_grf_funcs = {
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.reset = rk3568_edp_phy_grf_reset,
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};
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static const struct of_device_id rockchip_edp_phy_grf_match[] = {
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{
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.compatible = "rockchip,rk3568-edp-phy-grf",
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.data = &rk3568_edp_phy_grf_funcs,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, rockchip_edp_phy_grf_match);
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static struct platform_driver rockchip_edp_phy_grf_driver = {
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.driver = {
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.name = "rockchip-edp-phy-grf",
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.of_match_table = rockchip_edp_phy_grf_match,
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.pm = &rockchip_edp_phy_grf_pm_ops,
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},
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.probe = rockchip_edp_phy_grf_probe,
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};
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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struct rockchip_grf_value {
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const char *desc;
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u32 reg;
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u32 val;
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};
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struct rockchip_grf_info {
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const struct rockchip_grf_value *values;
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int num_values;
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};
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#define PX30_GRF_SOC_CON5 0x414
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static const struct rockchip_grf_value px30_defaults[] __initconst = {
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/*
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* Postponing auto jtag/sdmmc switching by 5 seconds.
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* The counter value is calculated based on 24MHz clock.
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*/
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{ "jtag switching delay", PX30_GRF_SOC_CON5, 0x7270E00},
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};
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static const struct rockchip_grf_info px30_grf __initconst = {
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.values = px30_defaults,
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.num_values = ARRAY_SIZE(px30_defaults),
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};
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#define RK3036_GRF_SOC_CON0 0x140
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static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
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/*
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* Disable auto jtag/sdmmc switching that causes issues with the
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* clock-framework and the mmc controllers making them unreliable.
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*/
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{ "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
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};
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static const struct rockchip_grf_info rk3036_grf __initconst = {
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.values = rk3036_defaults,
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.num_values = ARRAY_SIZE(rk3036_defaults),
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};
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#define RK3128_GRF_SOC_CON0 0x140
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static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
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{ "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
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};
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static const struct rockchip_grf_info rk3128_grf __initconst = {
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.values = rk3128_defaults,
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.num_values = ARRAY_SIZE(rk3128_defaults),
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};
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#define RK3228_GRF_SOC_CON6 0x418
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static const struct rockchip_grf_value rk3228_defaults[] __initconst = {
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{ "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
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};
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static const struct rockchip_grf_info rk3228_grf __initconst = {
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.values = rk3228_defaults,
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.num_values = ARRAY_SIZE(rk3228_defaults),
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};
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#define RK3288_GRF_SOC_CON0 0x244
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#define RK3288_GRF_SOC_CON2 0x24c
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static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
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{ "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
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{ "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
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};
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static const struct rockchip_grf_info rk3288_grf __initconst = {
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.values = rk3288_defaults,
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.num_values = ARRAY_SIZE(rk3288_defaults),
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};
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#define RK3328_GRF_SOC_CON4 0x410
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static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
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{ "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
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};
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static const struct rockchip_grf_info rk3328_grf __initconst = {
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.values = rk3328_defaults,
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.num_values = ARRAY_SIZE(rk3328_defaults),
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};
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#define RK3308_GRF_SOC_CON3 0x30c
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#define RK3308_GRF_SOC_CON13 0x608
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static const struct rockchip_grf_value rk3308_defaults[] __initconst = {
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{ "uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10) },
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{ "uart2 auto switching", RK3308_GRF_SOC_CON13, HIWORD_UPDATE(0, 0x1, 12) },
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};
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static const struct rockchip_grf_info rk3308_grf __initconst = {
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.values = rk3308_defaults,
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.num_values = ARRAY_SIZE(rk3308_defaults),
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};
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#define RK3368_GRF_SOC_CON15 0x43c
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static const struct rockchip_grf_value rk3368_defaults[] __initconst = {
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{ "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
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};
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static const struct rockchip_grf_info rk3368_grf __initconst = {
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.values = rk3368_defaults,
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.num_values = ARRAY_SIZE(rk3368_defaults),
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};
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#define RK3399_GRF_SOC_CON7 0xe21c
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static const struct rockchip_grf_value rk3399_defaults[] __initconst = {
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{ "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
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};
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static const struct rockchip_grf_info rk3399_grf __initconst = {
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.values = rk3399_defaults,
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.num_values = ARRAY_SIZE(rk3399_defaults),
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};
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#define RK3588_SYS_GRF_SOC_CON7 0x031c
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static const struct rockchip_grf_value rk3588_sys_grf_defaults[] __initconst = {
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{ "Connect EDP hpd to IO", RK3588_SYS_GRF_SOC_CON7, HIWORD_UPDATE(0x3, 0x3, 14) },
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};
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static const struct rockchip_grf_info rk3588_sys_grf __initconst = {
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.values = rk3588_sys_grf_defaults,
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.num_values = ARRAY_SIZE(rk3588_sys_grf_defaults),
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};
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#define DELAY_ONE_SECOND 0x16E3600
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#define RV1126_GRF1_SDDETFLT_CON 0x10254
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#define RV1126_GRF1_UART2RX_LOW_CON 0x10258
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#define RV1126_GRF1_IOFUNC_CON1 0x10264
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#define RV1126_GRF1_IOFUNC_CON3 0x1026C
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#define RV1126_JTAG_GROUP0 0x0 /* mux to sdmmc*/
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#define RV1126_JTAG_GROUP1 0x1 /* mux to uart2 */
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#define FORCE_JTAG_ENABLE 0x1
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#define FORCE_JTAG_DISABLE 0x0
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static const struct rockchip_grf_value rv1126_defaults[] __initconst = {
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{ "jtag group0 force", RV1126_GRF1_IOFUNC_CON3,
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HIWORD_UPDATE(FORCE_JTAG_DISABLE, 1, 4) },
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{ "jtag group1 force", RV1126_GRF1_IOFUNC_CON3,
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HIWORD_UPDATE(FORCE_JTAG_DISABLE, 1, 5) },
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{ "jtag group1 tms low delay", RV1126_GRF1_UART2RX_LOW_CON, DELAY_ONE_SECOND },
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{ "switch to jtag groupx", RV1126_GRF1_IOFUNC_CON1, HIWORD_UPDATE(RV1126_JTAG_GROUP0, 1, 15) },
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{ "jtag group0 switching delay", RV1126_GRF1_SDDETFLT_CON, DELAY_ONE_SECOND * 5 },
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};
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static const struct rockchip_grf_info rv1126_grf __initconst = {
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.values = rv1126_defaults,
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.num_values = ARRAY_SIZE(rv1126_defaults),
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};
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static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
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{
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.compatible = "rockchip,px30-grf",
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.data = (void *)&px30_grf,
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}, {
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.compatible = "rockchip,rk3036-grf",
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.data = (void *)&rk3036_grf,
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}, {
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.compatible = "rockchip,rk3128-grf",
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.data = (void *)&rk3128_grf,
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}, {
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.compatible = "rockchip,rk3228-grf",
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.data = (void *)&rk3228_grf,
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}, {
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.compatible = "rockchip,rk3288-grf",
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.data = (void *)&rk3288_grf,
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}, {
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.compatible = "rockchip,rk3308-grf",
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.data = (void *)&rk3308_grf,
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}, {
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.compatible = "rockchip,rk3328-grf",
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.data = (void *)&rk3328_grf,
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}, {
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.compatible = "rockchip,rk3368-grf",
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.data = (void *)&rk3368_grf,
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}, {
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.compatible = "rockchip,rk3399-grf",
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.data = (void *)&rk3399_grf,
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}, {
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.compatible = "rockchip,rk3588-sys-grf",
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.data = (void *)&rk3588_sys_grf,
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}, {
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.compatible = "rockchip,rv1126-grf",
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.data = (void *)&rv1126_grf,
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},
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{ /* sentinel */ },
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};
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static int __init rockchip_grf_init(void)
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{
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const struct rockchip_grf_info *grf_info;
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const struct of_device_id *match;
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struct device_node *np;
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struct regmap *grf;
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int ret, i;
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ret = platform_driver_register(&rockchip_edp_phy_grf_driver);
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if (ret)
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return ret;
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np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match,
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&match);
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if (!np)
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return 0;
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if (!match || !match->data) {
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pr_err("%s: missing grf data\n", __func__);
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of_node_put(np);
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return -EINVAL;
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}
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grf_info = match->data;
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grf = syscon_node_to_regmap(np);
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of_node_put(np);
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if (IS_ERR(grf)) {
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pr_err("%s: could not get grf syscon\n", __func__);
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return PTR_ERR(grf);
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}
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for (i = 0; i < grf_info->num_values; i++) {
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const struct rockchip_grf_value *val = &grf_info->values[i];
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pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
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val->desc, val->reg, val->val);
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ret = regmap_write(grf, val->reg, val->val);
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if (ret < 0)
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pr_err("%s: write to %#6x failed with %d\n",
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__func__, val->reg, ret);
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}
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return 0;
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}
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postcore_initcall(rockchip_grf_init);
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MODULE_DESCRIPTION("Rockchip GRF");
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MODULE_LICENSE("GPL");
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