/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Rockchip MIPI CSI2 DPHY driver
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*
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* Copyright (C) 2020 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_
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#define _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_
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#include <linux/rk-camera-module.h>
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#include <linux/rkcif-config.h>
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#define PHY_MAX 16
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#define MAX_DEV_NAME_LEN 32
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#define MAX_SAMSUNG_PHY_NUM 2
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#define MAX_INNO_PHY_NUM 2
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/* add new chip id in tail by time order */
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enum csi2_dphy_chip_id {
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CHIP_ID_RK3568 = 0x0,
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CHIP_ID_RK3588 = 0x1,
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CHIP_ID_RK3588_DCPHY = 0x2,
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CHIP_ID_RV1106 = 0x3,
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CHIP_ID_RK3562 = 0x4,
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};
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enum csi2_dphy_rx_pads {
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CSI2_DPHY_RX_PAD_SINK = 0,
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CSI2_DPHY_RX_PAD_SOURCE,
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CSI2_DPHY_RX_PADS_NUM,
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};
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enum csi2_dphy_lane_mode {
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LANE_MODE_UNDEF = 0x0,
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LANE_MODE_FULL,
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LANE_MODE_SPLIT,
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};
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struct grf_reg {
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u32 offset;
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u32 mask;
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u32 shift;
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};
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struct csi2dphy_reg {
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u32 offset;
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};
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#define MAX_DPHY_SENSORS (2)
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#define MAX_NUM_CSI2_DPHY (0x2)
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struct csi2_sensor {
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struct v4l2_subdev *sd;
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struct v4l2_mbus_config mbus;
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struct v4l2_mbus_framefmt format;
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int lanes;
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};
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struct csi2_dphy_hw;
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struct samsung_mipi_dcphy;
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struct dphy_drv_data {
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const char dev_name[MAX_DEV_NAME_LEN];
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enum csi2_dphy_chip_id chip_id;
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char num_inno_phy;
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char num_samsung_phy;
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};
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struct csi2_dphy {
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struct device *dev;
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struct list_head list;
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struct csi2_dphy_hw *dphy_hw;
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struct csi2_dphy_hw *dphy_hw_group[MAX_INNO_PHY_NUM];
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struct samsung_mipi_dcphy *samsung_phy;
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struct samsung_mipi_dcphy *samsung_phy_group[MAX_SAMSUNG_PHY_NUM];
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struct v4l2_async_notifier notifier;
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struct v4l2_subdev sd;
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struct mutex mutex; /* lock for updating protection */
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struct media_pad pads[CSI2_DPHY_RX_PADS_NUM];
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struct csi2_sensor sensors[MAX_DPHY_SENSORS];
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u64 data_rate_mbps;
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int num_sensors;
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int phy_index;
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struct rkcif_csi_info csi_info;
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void *phy_hw[RKMODULE_MULTI_DEV_NUM];
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bool is_streaming;
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int lane_mode;
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const struct dphy_drv_data *drv_data;
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struct rkmodule_csi_dphy_param dphy_param;
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};
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struct dphy_hw_drv_data {
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const struct hsfreq_range *hsfreq_ranges;
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int num_hsfreq_ranges;
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const struct hsfreq_range *hsfreq_ranges_cphy;
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int num_hsfreq_ranges_cphy;
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const struct grf_reg *grf_regs;
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const struct txrx_reg *txrx_regs;
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const struct csi2dphy_reg *csi2dphy_regs;
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void (*individual_init)(struct csi2_dphy_hw *hw);
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int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
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int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
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enum csi2_dphy_chip_id chip_id;
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};
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struct csi2_dphy_hw {
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struct device *dev;
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struct regmap *regmap_grf;
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struct regmap *regmap_sys_grf;
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const struct grf_reg *grf_regs;
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const struct txrx_reg *txrx_regs;
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const struct csi2dphy_reg *csi2dphy_regs;
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const struct dphy_hw_drv_data *drv_data;
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void __iomem *hw_base_addr;
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struct clk_bulk_data *clks_bulk;
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struct reset_control *rsts_bulk;
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struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY];
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struct v4l2_subdev sd;
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struct mutex mutex; /* lock for updating protection */
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atomic_t stream_cnt;
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int num_clks;
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int num_sensors;
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int dphy_dev_num;
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enum csi2_dphy_lane_mode lane_mode;
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int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
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int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd);
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int (*ttl_mode_enable)(struct csi2_dphy_hw *hw);
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void (*ttl_mode_disable)(struct csi2_dphy_hw *hw);
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};
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int rockchip_csi2_dphy_hw_init(void);
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int rockchip_csi2_dphy_init(void);
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#endif
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