/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright © 2015 Broadcom Corporation
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*/
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#ifndef __BRCMNAND_H__
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#define __BRCMNAND_H__
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#include <linux/types.h>
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#include <linux/io.h>
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struct platform_device;
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struct dev_pm_ops;
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struct brcmnand_soc {
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bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
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void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
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void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare,
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bool is_param);
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};
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static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc,
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bool is_param)
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{
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if (soc && soc->prepare_data_bus)
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soc->prepare_data_bus(soc, true, is_param);
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}
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static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc,
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bool is_param)
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{
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if (soc && soc->prepare_data_bus)
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soc->prepare_data_bus(soc, false, is_param);
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}
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static inline u32 brcmnand_readl(void __iomem *addr)
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{
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/*
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* MIPS endianness is configured by boot strap, which also reverses all
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* bus endianness (i.e., big-endian CPU + big endian bus ==> native
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* endian I/O).
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*
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* Other architectures (e.g., ARM) either do not support big endian, or
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* else leave I/O in little endian mode.
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*/
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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return __raw_readl(addr);
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else
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return readl_relaxed(addr);
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}
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static inline void brcmnand_writel(u32 val, void __iomem *addr)
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{
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/* See brcmnand_readl() comments */
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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__raw_writel(val, addr);
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else
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writel_relaxed(val, addr);
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}
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int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc);
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int brcmnand_remove(struct platform_device *pdev);
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extern const struct dev_pm_ops brcmnand_pm_ops;
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#endif /* __BRCMNAND_H__ */
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