/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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*
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* Author: Chen Shunqing <csq@rock-chips.com>
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*/
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#ifndef HDMIRX_H
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#define HDMIRX_H
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#include "rk628.h"
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#define HDMIRX_REG(x) ((x) + 0x30000)
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/* --------- EDID and HDCP KEY ------- */
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#define EDID_BASE 0x000a0000
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#define HDCP_KEY_BASE 0x000a8000
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#define KEY_MAX_REGISTER 0x000a8490
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#define HDMI_RX_HDMI_SETUP_CTRL HDMIRX_REG(0x0000)
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#define HOT_PLUG_DETECT_MASK BIT(0)
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#define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0)
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#define HDMI_RX_HDMI_OVR_CTRL HDMIRX_REG(0x0004)
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#define HDMI_RX_HDMI_TIMER_CTRL HDMIRX_REG(0x0008)
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#define HDMI_RX_HDMI_RES_OVR HDMIRX_REG(0x0010)
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#define HDMI_RX_HDMI_RES_STS HDMIRX_REG(0x0014)
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#define HDMI_RX_HDMI_PLL_CTRL HDMIRX_REG(0x0018)
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#define HDMI_RX_HDMI_PLL_FRQSET1 HDMIRX_REG(0x001c)
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#define HDMI_RX_HDMI_PLL_FRQSET2 HDMIRX_REG(0x0020)
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#define HDMI_RX_HDMI_PLL_PAR1 HDMIRX_REG(0x0024)
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#define HDMI_RX_HDMI_PLL_PAR2 HDMIRX_REG(0x0028)
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#define HDMI_RX_HDMI_PLL_PAR3 HDMIRX_REG(0x002c)
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#define HDMI_RX_HDMI_PLL_LCK_STS HDMIRX_REG(0x0030)
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#define HDMI_RX_HDMI_CLK_CTRL HDMIRX_REG(0x0034)
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#define HDMI_RX_HDMI_PCB_CTRL HDMIRX_REG(0x0038)
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#define SEL_PIXCLKSRC_MASK GENMASK(19, 18)
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#define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18)
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#define HDMI_RX_HDMI_PHS_CTR HDMIRX_REG(0x0040)
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#define HDMI_RX_HDMI_PHS_USED HDMIRX_REG(0x0044)
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#define HDMI_RX_HDMI_MISC_CTRL HDMIRX_REG(0x0048)
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#define HDMI_RX_HDMI_EQOFF_CTRL HDMIRX_REG(0x004c)
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#define HDMI_RX_HDMI_EQGAIN_CTRL HDMIRX_REG(0x0050)
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#define HDMI_RX_HDMI_EQCAL_STS HDMIRX_REG(0x0054)
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#define HDMI_RX_HDMI_EQRESULT HDMIRX_REG(0x0058)
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#define HDMI_RX_HDMI_EQ_MEAS_CTRL HDMIRX_REG(0x005c)
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#define HDMI_RX_HDMI_WR_CFG HDMIRX_REG(0x0060)
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#define HDMI_RX_HDMI_CTRL HDMIRX_REG(0x0064)
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#define HDMI_RX_HDMI_MODE_RECOVER HDMIRX_REG(0x0080)
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#define PREAMBLE_CNT_LIMIT_MASK GENMASK(31, 27)
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#define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27)
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#define OESSCTL3_THR_MASK GENMASK(20, 19)
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#define OESSCTL3_THR(x) UPDATE(x, 20, 19)
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#define SPIKE_FILTER_EN_MASK BIT(18)
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#define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18)
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#define DVI_MODE_HYST_MASK GENMASK(17, 13)
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#define DVI_MODE_HYST(x) UPDATE(x, 17, 13)
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#define HDMI_MODE_HYST_MASK GENMASK(12, 8)
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#define HDMI_MODE_HYST(x) UPDATE(x, 12, 8)
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#define HDMI_MODE_MASK GENMASK(7, 6)
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#define HDMI_MODE(x) UPDATE(x, 7, 6)
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#define GB_DET_MASK GENMASK(5, 4)
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#define GB_DET(x) UPDATE(x, 5, 4)
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#define EESS_OESS_MASK GENMASK(3, 2)
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#define EESS_OESS(x) UPDATE(x, 3, 2)
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#define SEL_CTL01_MASK GENMASK(1, 0)
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#define SEL_CTL01(x) UPDATE(x, 1, 0)
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#define HDMI_RX_HDMI_ERROR_PROTECT HDMIRX_REG(0x0084)
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#define RG_BLOCK_OFF_MASK BIT(20)
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#define RG_BLOCK_OFF(x) UPDATE(x, 20, 20)
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#define BLOCK_OFF_MASK BIT(19)
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#define BLOCK_OFF(x) UPDATE(x, 19, 19)
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#define VALID_MODE_MASK GENMASK(18, 16)
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#define VALID_MODE(x) UPDATE(x, 18, 16)
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#define CTRL_FILT_SEN_MASK GENMASK(13, 12)
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#define CTRL_FILT_SEN(x) UPDATE(x, 13, 12)
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#define VS_FILT_SENS_MASK GENMASK(11, 10)
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#define VS_FILT_SENS(x) UPDATE(x, 11, 10)
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#define HS_FILT_SENS_MASK GENMASK(9, 8)
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#define HS_FILT_SENS(x) UPDATE(x, 9, 8)
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#define DE_MEASURE_MODE_MASK GENMASK(7, 6)
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#define DE_MEASURE_MODE(x) UPDATE(x, 7, 6)
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#define DE_REGEN_MASK BIT(5)
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#define DE_REGEN(x) UPDATE(x, 5, 5)
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#define DE_FILTER_SENS_MASK GENMASK(4, 3)
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#define DE_FILTER_SENS(x) UPDATE(x, 4, 3)
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#define HDMI_RX_HDMI_ERD_STS HDMIRX_REG(0x0088)
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#define HDMI_RX_HDMI_SYNC_CTRL HDMIRX_REG(0x0090)
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#define VS_POL_ADJ_MODE_MASK GENMASK(4, 3)
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#define VS_POL_ADJ_MODE(x) UPDATE(x, 4, 3)
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#define HS_POL_ADJ_MODE_MASK GENMASK(2, 1)
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#define HS_POL_ADJ_MODE(x) UPDATE(x, 2, 1)
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#define HDMI_RX_HDMI_CKM_EVLTM HDMIRX_REG(0x0094)
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#define LOCK_HYST_MASK GENMASK(21, 20)
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#define LOCK_HYST(x) UPDATE(x, 21, 20)
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#define CLK_HYST_MASK GENMASK(18, 16)
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#define CLK_HYST(x) UPDATE(x, 18, 16)
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#define EVAL_TIME_MASK GENMASK(15, 4)
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#define EVAL_TIME(x) UPDATE(x, 15, 4)
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#define HDMI_RX_HDMI_CKM_F HDMIRX_REG(0x0098)
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#define HDMIRX_MAXFREQ_MASK GENMASK(31, 16)
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#define HDMIRX_MAXFREQ(x) UPDATE(x, 31, 16)
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#define MINFREQ_MASK GENMASK(15, 0)
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#define MINFREQ(x) UPDATE(x, 15, 0)
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#define HDMI_RX_HDMI_CKM_RESULT HDMIRX_REG(0x009c)
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#define HDMI_RX_HDMI_PVO_CONFIG HDMIRX_REG(0x00a0)
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#define HDMI_RX_HDMI_RESMPL_CTRL HDMIRX_REG(0x00a4)
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#define MAN_VID_DEREPEAT_MASK GENMASK(4, 1)
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#define MAN_VID_DEREPEAT(x) UPDATE(x, 4, 1)
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#define AUTO_DEREPEAT_MASK BIT(0)
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#define AUTO_DEREPEAT(x) UPDATE(x, 0, 0)
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#define HDMI_RX_HDMI_DCM_CTRL HDMIRX_REG(0x00a8)
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#define DCM_DEFAULT_PHASE_MASK BIT(18)
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#define DCM_DEFAULT_PHASE(x) UPDATE(x, 18, 18)
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#define DCM_COLOUR_DEPTH_SEL_MASK BIT(12)
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#define DCM_COLOUR_DEPTH_SEL(x) UPDATE(x, 12, 12)
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#define DCM_COLOUR_DEPTH_MASK GENMASK(11, 8)
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#define DCM_COLOUR_DEPTH(x) UPDATE(x, 11, 8)
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#define DCM_GCP_ZERO_FIELDS_MASK GENMASK(5, 2)
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#define DCM_GCP_ZERO_FIELDS(x) UPDATE(x, 5, 2)
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#define HDMI_RX_HDMI_VM_CFG_CH_0_1 HDMIRX_REG(0x00b0)
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#define HDMI_RX_HDMI_VM_CFG_CH2 HDMIRX_REG(0x00b4)
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#define HDMI_RX_HDMI_SPARE HDMIRX_REG(0x00b8)
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#define HDMI_RX_HDMI_STS HDMIRX_REG(0x00bc)
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#define HDMI_RX_HDCP_CTRL HDMIRX_REG(0x00c0)
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#define HDCP_ENABLE_MASK BIT(24)
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#define HDCP_ENABLE(x) UPDATE(x, 24, 24)
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#define FREEZE_HDCP_FSM_MASK BIT(21)
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#define FREEZE_HDCP_FSM(x) UPDATE(x, 21, 21)
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#define FREEZE_HDCP_STATE_MASK GENMASK(20, 15)
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#define FREEZE_HDCP_STATE(x) UPDATE(x, 20, 15)
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#define HDCP_CTL_MASK GENMASK(9, 8)
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#define HDCP_CTL(x) UPDATE(x, 9, 8)
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#define HDCP_RI_RATE_MASK GENMASK(7, 6)
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#define HDCP_RI_RATE(x) UPDATE(x, 7, 6)
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#define KEY_DECRYPT_ENABLE_MASK BIT(1)
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#define KEY_DECRYPT_ENABLE(x) UPDATE(x, 1, 1)
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#define HDCP_ENC_EN_MASK BIT(0)
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#define HDCP_ENC_EN(x) UPDATE(x, 0, 0)
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#define HDMI_RX_HDCP_SETTINGS HDMIRX_REG(0x00c4)
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#define HDMI_RESERVED(x) UPDATE(x, 13, 13)
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#define HDMI_RESERVED_MASK BIT(13)
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#define FAST_I2C(x) UPDATE(x, 12, 12)
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#define FAST_I2C_MASK BIT(12)
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#define ONE_DOT_ONE(x) UPDATE(x, 9, 9)
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#define ONE_DOT_ONE_MASK BIT(9)
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#define FAST_REAUTH(x) UPDATE(x, 8, 8)
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#define FAST_REAUTH_MASK BIT(8)
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#define HDMI_RX_HDCP_SEED HDMIRX_REG(0x00c8)
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#define HDMI_RX_HDCP_BKSV1 HDMIRX_REG(0x00cc)
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#define HDMI_RX_HDCP_BKSV0 HDMIRX_REG(0x00d0)
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#define HDMI_RX_HDCP_KIDX HDMIRX_REG(0x00d4)
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#define HDMI_RX_HDCP_KEY1 HDMIRX_REG(0x00d8)
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#define HDMI_RX_HDCP_KEY0 HDMIRX_REG(0x00dc)
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#define HDMI_RX_HDCP_DBG HDMIRX_REG(0x00e0)
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#define HDMI_RX_HDCP_AKSV1 HDMIRX_REG(0x00e4)
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#define HDMI_RX_HDCP_AKSV0 HDMIRX_REG(0x00e8)
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#define HDMI_RX_HDCP_AN1 HDMIRX_REG(0x00ec)
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#define HDMI_RX_HDCP_AN0 HDMIRX_REG(0x00f0)
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#define HDMI_RX_HDCP_EESS_WOO HDMIRX_REG(0x00f4)
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#define HDMI_RX_HDCP_I2C_TIMEOUT HDMIRX_REG(0x00f8)
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#define HDMI_RX_HDCP_STS HDMIRX_REG(0x00fc)
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#define HDMI_RX_MD_HCTRL1 HDMIRX_REG(0x0140)
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#define HACT_PIX_ITH_MASK GENMASK(10, 8)
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#define HACT_PIX_ITH(x) UPDATE(x, 10, 8)
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#define HACT_PIX_SRC_MASK BIT(5)
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#define HACT_PIX_SRC(x) UPDATE(x, 5, 5)
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#define HTOT_PIX_SRC_MASK BIT(4)
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#define HTOT_PIX_SRC(x) UPDATE(x, 4, 4)
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#define HDMI_RX_MD_HCTRL2 HDMIRX_REG(0x0144)
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#define HS_CLK_ITH_MASK GENMASK(14, 12)
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#define HS_CLK_ITH(x) UPDATE(x, 14, 12)
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#define HTOT32_CLK_ITH_MASK GENMASK(9, 8)
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#define HTOT32_CLK_ITH(x) UPDATE(x, 9, 8)
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#define VS_ACT_TIME_MASK BIT(5)
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#define VS_ACT_TIME(x) UPDATE(x, 5, 5)
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#define HS_ACT_TIME_MASK GENMASK(4, 3)
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#define HS_ACT_TIME(x) UPDATE(x, 4, 3)
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#define H_START_POS_MASK GENMASK(1, 0)
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#define H_START_POS(x) UPDATE(x, 1, 0)
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#define HDMI_RX_MD_HT0 HDMIRX_REG(0x0148)
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#define HDMI_RX_MD_HT1 HDMIRX_REG(0x014c)
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#define HDMI_RX_MD_HACT_PX HDMIRX_REG(0x0150)
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#define HDMI_RX_MD_HACT_RSV HDMIRX_REG(0x0154)
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#define HDMI_RX_MD_VCTRL HDMIRX_REG(0x0158)
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#define V_OFFS_LIN_MODE_MASK BIT(4)
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#define V_OFFS_LIN_MODE(x) UPDATE(x, 4, 4)
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#define V_EDGE_MASK BIT(1)
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#define V_EDGE(x) UPDATE(x, 1, 1)
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#define V_MODE_MASK BIT(0)
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#define V_MODE(x) UPDATE(x, 0, 0)
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#define HDMI_RX_MD_VSC HDMIRX_REG(0x015c)
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#define HDMI_RX_MD_VTC HDMIRX_REG(0x0160)
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#define HDMI_RX_MD_VOL HDMIRX_REG(0x0164)
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#define HDMI_RX_MD_VAL HDMIRX_REG(0x0168)
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#define HDMI_RX_MD_VTH HDMIRX_REG(0x016c)
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#define VOFS_LIN_ITH_MASK GENMASK(11, 10)
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#define VOFS_LIN_ITH(x) UPDATE(x, 11, 10)
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#define VACT_LIN_ITH_MASK GENMASK(9, 8)
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#define VACT_LIN_ITH(x) UPDATE(x, 9, 8)
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#define VTOT_LIN_ITH_MASK GENMASK(7, 6)
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#define VTOT_LIN_ITH(x) UPDATE(x, 7, 6)
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#define VS_CLK_ITH_MASK GENMASK(5, 3)
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#define VS_CLK_ITH(x) UPDATE(x, 5, 3)
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#define VTOT_CLK_ITH_MASK GENMASK(2, 0)
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#define VTOT_CLK_ITH(x) UPDATE(x, 2, 0)
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#define HDMI_RX_MD_VTL HDMIRX_REG(0x0170)
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#define HDMI_RX_MD_IL_CTRL HDMIRX_REG(0x0174)
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#define HDMI_RX_MD_IL_SKEW HDMIRX_REG(0x0178)
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#define HDMI_RX_MD_IL_POL HDMIRX_REG(0x017c)
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#define FAFIELDDET_EN_MASK BIT(2)
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#define FAFIELDDET_EN(x) UPDATE(x, 2, 2)
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#define FIELD_POL_MODE_MASK GENMASK(1, 0)
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#define FIELD_POL_MODE(x) UPDATE(x, 1, 0)
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#define HDMI_RX_MD_STS HDMIRX_REG(0x0180)
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#define ILACE_STS BIT(3)
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#define HDMI_RX_AUD_CTRL HDMIRX_REG(0x0200)
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#define HDMI_RX_AUD_PLL_CTRL HDMIRX_REG(0x0208)
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#define PLL_LOCK_TOGGLE_DIV_MASK GENMASK(27, 24)
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#define PLL_LOCK_TOGGLE_DIV(x) UPDATE(x, 27, 24)
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#define HDMI_RX_AUD_CLK_CTRL HDMIRX_REG(0x0214)
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#define CTS_N_REF_MASK BIT(4)
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#define CTS_N_REF(x) UPDATE(x, 4, 4)
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#define HDMI_RX_AUD_CLK_STS HDMIRX_REG(0x023c)
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#define HDMI_RX_AUD_FIFO_CTRL HDMIRX_REG(0x0240)
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#define AFIF_SUBPACKET_DESEL_MASK GENMASK(27, 24)
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#define AFIF_SUBPACKET_DESEL(x) UPDATE(x, 27, 24)
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#define AFIF_SUBPACKETS_MASK BIT(16)
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#define AFIF_SUBPACKETS(x) UPDATE(x, 16, 16)
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#define MSA_CHANNEL_DESELECT BIT(24)
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#define HDMI_RX_AUD_FIFO_TH HDMIRX_REG(0x0244)
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#define AFIF_TH_START_MASK GENMASK(26, 18)
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#define AFIF_TH_START(x) UPDATE(x, 26, 18)
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#define AFIF_TH_MAX_MASK GENMASK(17, 9)
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#define AFIF_TH_MAX(x) UPDATE(x, 17, 9)
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#define AFIF_TH_MIN_MASK GENMASK(8, 0)
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#define AFIF_TH_MIN(x) UPDATE(x, 8, 0)
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#define HDMI_RX_AUD_FIFO_FILL_S HDMIRX_REG(0x0248)
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#define HDMI_RX_AUD_FIFO_CLR_MM HDMIRX_REG(0x024c)
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#define HDMI_RX_AUD_FIFO_FILLSTS HDMIRX_REG(0x0250)
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#define HDMI_RX_AUD_CHEXTR_CTRL HDMIRX_REG(0x0254)
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#define AUD_LAYOUT_CTRL(x) UPDATE(x, 1, 0)
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#define HDMI_RX_AUD_MUTE_CTRL HDMIRX_REG(0x0258)
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#define APPLY_INT_MUTE_MASK BIT(31)
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#define APPLY_INT_MUTE(x) UPDATE(x, 31, 31)
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#define APORT_SHDW_CTRL_MASK GENMASK(22, 21)
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#define APORT_SHDW_CTRL(x) UPDATE(x, 22, 21)
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#define AUTO_ACLK_MUTE_MASK GENMASK(20, 19)
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#define AUTO_ACLK_MUTE(x) UPDATE(x, 20, 19)
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#define AUD_MUTE_SPEED_MASK GENMASK(16, 10)
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#define AUD_MUTE_SPEED(x) UPDATE(x, 16, 10)
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#define AUD_AVMUTE_EN_MASK BIT(7)
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#define AUD_AVMUTE_EN(x) UPDATE(x, 7, 7)
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#define AUD_MUTE_SEL_MASK GENMASK(6, 5)
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#define AUD_MUTE_SEL(x) UPDATE(x, 6, 5)
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#define AUD_MUTE_MODE_MASK GENMASK(4, 3)
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#define AUD_MUTE_MODE(x) UPDATE(x, 4, 3)
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#define HDMI_RX_AUD_FIFO_FILLSTS1 HDMIRX_REG(0x025c)
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#define HDMI_RX_AUD_SAO_CTRL HDMIRX_REG(0x0260)
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#define I2S_LPCM_BPCUV_MASK BIT(11)
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#define I2S_LPCM_BPCUV(x) UPDATE(x, 11, 11)
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#define I2S_32_16_MASK BIT(0)
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#define I2S_32_16(x) UPDATE(x, 0, 0)
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#define HDMI_RX_AUD_PAO_CTRL HDMIRX_REG(0x0264)
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#define PAO_RATE_MASK GENMASK(17, 16)
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#define PAO_RATE(x) UPDATE(x, 17, 16)
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#define HDMI_RX_AUD_SPARE HDMIRX_REG(0x0268)
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#define HDMI_RX_AUD_FIFO_STS HDMIRX_REG(0x027c)
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#define HDMI_RX_AUDPLL_GEN_CTS HDMIRX_REG(0x0280)
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#define AUDPLL_CTS_MANUAL(x) UPDATE(x, 19, 0)
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#define HDMI_RX_AUDPLL_GEN_N HDMIRX_REG(0x0284)
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#define AUDPLL_N_MANUAL(x) UPDATE(x, 19, 0)
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#define HDMI_RX_AUDPLL_GEN_CTRL_RW1 HDMIRX_REG(0x0288)
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#define HDMI_RX_AUDPLL_GEN_CTRL_RW2 HDMIRX_REG(0x028c)
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#define HDMI_RX_AUDPLL_GEN_CTRL_W1 HDMIRX_REG(0x0298)
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#define HDMI_RX_AUDPLL_GEN_STS_RO1 HDMIRX_REG(0x02a0)
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#define HDMI_RX_AUDPLL_GEN_STS_RO2 HDMIRX_REG(0x02a4)
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#define HDMI_RX_AUDPLL_SC_NDIVCTSTH HDMIRX_REG(0x02a8)
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#define HDMI_RX_AUDPLL_SC_CTS HDMIRX_REG(0x02ac)
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#define HDMI_RX_AUDPLL_SC_N HDMIRX_REG(0x02b0)
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#define HDMI_RX_AUDPLL_SC_CTRL HDMIRX_REG(0x02b4)
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#define HDMI_RX_AUDPLL_SC_STS1 HDMIRX_REG(0x02b8)
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#define HDMI_RX_AUDPLL_SC_STS2 HDMIRX_REG(0x02bc)
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#define HDMI_RX_SNPS_PHYG3_CTRL HDMIRX_REG(0x02c0)
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#define PORTSELECT_MASK GENMASK(3, 2)
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#define PORTSELECT(x) UPDATE(x, 3, 2)
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#define HDMI_RX_I2CM_PHYG3_SLAVE HDMIRX_REG(0x02c4)
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#define HDMI_RX_I2CM_PHYG3_ADDRESS HDMIRX_REG(0x02c8)
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#define HDMI_RX_I2CM_PHYG3_DATAO HDMIRX_REG(0x02cc)
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#define HDMI_RX_I2CM_PHYG3_DATAI HDMIRX_REG(0x02d0)
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#define HDMI_RX_I2CM_PHYG3_OPERATION HDMIRX_REG(0x02d4)
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#define HDMI_RX_I2CM_PHYG3_MODE HDMIRX_REG(0x02d8)
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#define HDMI_RX_I2CM_PHYG3_SOFTRST HDMIRX_REG(0x02dc)
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#define HDMI_RX_I2CM_PHYG3_SS_CNTS HDMIRX_REG(0x02e0)
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#define HDMI_RX_I2CM_PHYG3_FS_HCNT HDMIRX_REG(0x02e4)
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#define HDMI_RX_JTAG_CONF HDMIRX_REG(0x02ec)
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#define HDMI_RX_JTAG_TAP_TCLK HDMIRX_REG(0x02f0)
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#define HDMI_RX_JTAG_TAP_IN HDMIRX_REG(0x02f4)
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#define HDMI_RX_JTAG_TAP_OUT HDMIRX_REG(0x02f8)
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#define HDMI_RX_JTAG_ADDR HDMIRX_REG(0x02fc)
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#define HDMI_RX_PDEC_CTRL HDMIRX_REG(0x0300)
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#define PFIFO_SCORE_FILTER_EN BIT(31)
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#define PFIFO_SCORE_HDP_IF BIT(29)
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#define PFIFO_SCORE_AMP_IF BIT(28)
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#define PFIFO_SCORE_NTSCVBI_IF BIT(27)
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#define PFIFO_SCORE_MPEGS_IF BIT(26)
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#define PFIFO_SCORE_AUD_IF BIT(25)
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#define PFIFO_SCORE_SPD_IF BIT(24)
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#define PFIFO_SCORE_AVI_IF BIT(23)
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#define PFIFO_SCORE_VS_IF BIT(22)
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#define PFIFO_SCORE_GMTP BIT(21)
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#define PFIFO_SCORE_ISRC2 BIT(20)
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#define PFIFO_SCORE_ISRC1 BIT(19)
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#define PFIFO_SCORE_ACP BIT(18)
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#define PFIFO_SCORE_GCP BIT(17)
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#define PFIFO_SCORE_ACR BIT(16)
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#define GCP_GLOBAVMUTE BIT(15)
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#define PD_FIFO_WE BIT(4)
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#define PDEC_BCH_EN BIT(0)
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#define HDMI_RX_PDEC_FIFO_CFG HDMIRX_REG(0x0304)
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#define PD_FIFO_TH_START_MASK GENMASK(29, 20)
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#define PD_FIFO_TH_START(x) UPDATE(x, 29, 20)
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#define PD_FIFO_TH_MAX_MASK GENMASK(19, 10)
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#define PD_FIFO_TH_MAX(x) UPDATE(x, 19, 10)
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#define PD_FIFO_TH_MIN_MASK GENMASK(9, 0)
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#define PD_FIFO_TH_MIN(x) UPDATE(x, 9, 0)
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#define HDMI_RX_PDEC_FIFO_STS HDMIRX_REG(0x0308)
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#define HDMI_RX_PDEC_FIFO_DATA HDMIRX_REG(0x030c)
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#define HDMI_RX_PDEC_AUDIODET_CTRL HDMIRX_REG(0x0310)
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#define AUDIODET_THRESHOLD_MASK GENMASK(13, 9)
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#define AUDIODET_THRESHOLD(x) UPDATE(x, 13, 9)
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#define HDMI_RX_PDEC_DBG_ACP HDMIRX_REG(0x031c)
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#define HDMI_RX_PDEC_DBG_ERR_CORR HDMIRX_REG(0x0320)
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#define HDMI_RX_PDEC_FIFO_STS1 HDMIRX_REG(0x0324)
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#define HDMI_RX_PDEC_ACRM_CTRL HDMIRX_REG(0x0330)
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#define DELTACTS_IRQTRIG_MASK GENMASK(4, 2)
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#define DELTACTS_IRQTRIG(x) UPDATE(x, 4, 2)
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#define HDMI_RX_PDEC_ACRM_MAX HDMIRX_REG(0x0334)
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#define HDMI_RX_PDEC_ACRM_MIN HDMIRX_REG(0x0338)
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#define HDMI_RX_PDEC_ERR_FILTER HDMIRX_REG(0x033c)
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#define HDMI_RX_PDEC_ASP_CTRL HDMIRX_REG(0x0340)
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#define HDMI_RX_PDEC_ASP_ERR HDMIRX_REG(0x0344)
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#define HDMI_RX_PDEC_STS HDMIRX_REG(0x0360)
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#define HDMI_RX_PDEC_AUD_STS HDMIRX_REG(0x0364)
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#define HDMI_RX_PDEC_VSI_PAYLOAD0 HDMIRX_REG(0x0368)
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#define HDMI_RX_PDEC_VSI_PAYLOAD1 HDMIRX_REG(0x036c)
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#define HDMI_RX_PDEC_VSI_PAYLOAD2 HDMIRX_REG(0x0370)
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#define HDMI_RX_PDEC_VSI_PAYLOAD3 HDMIRX_REG(0x0374)
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#define HDMI_RX_PDEC_VSI_PAYLOAD4 HDMIRX_REG(0x0378)
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#define HDMI_RX_PDEC_VSI_PAYLOAD5 HDMIRX_REG(0x037c)
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#define HDMI_RX_PDEC_GCP_AVMUTE HDMIRX_REG(0x0380)
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#define PKTDEC_GCP_CD_MASK GENMASK(7, 4)
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#define HDMI_RX_PDEC_ACR_CTS HDMIRX_REG(0x0390)
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#define HDMI_RX_PDEC_ACR_N HDMIRX_REG(0x0394)
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#define HDMI_RX_PDEC_AVI_HB HDMIRX_REG(0x03a0)
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#define HDMI_RX_PDEC_AVI_PB HDMIRX_REG(0x03a4)
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#define VID_IDENT_CODE_VIC7 BIT(31)
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#define VID_IDENT_CODE GENMASK(30, 24)
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#define VIDEO_FORMAT GENMASK(6, 5)
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#define HDMI_RX_PDEC_AVI_TBB HDMIRX_REG(0x03a8)
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#define HDMI_RX_PDEC_AVI_LRB HDMIRX_REG(0x03ac)
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#define HDMI_RX_PDEC_AIF_CTRL HDMIRX_REG(0x03c0)
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#define FC_LFE_EXCHG BIT(18)
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#define HDMI_RX_PDEC_AIF_HB HDMIRX_REG(0x03c4)
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#define HDMI_RX_PDEC_AIF_PB0 HDMIRX_REG(0x03c8)
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#define HDMI_RX_PDEC_AIF_PB1 HDMIRX_REG(0x03cc)
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#define HDMI_RX_PDEC_GMD_HB HDMIRX_REG(0x03d0)
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#define HDMI_RX_PDEC_GMD_PB HDMIRX_REG(0x03d4)
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#define HDMI_RX_PDEC_VSI_ST0 HDMIRX_REG(0x03e0)
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#define HDMI_RX_PDEC_VSI_ST1 HDMIRX_REG(0x03e4)
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#define HDMI_RX_PDEC_VSI_PB0 HDMIRX_REG(0x03e8)
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#define HDMI_RX_PDEC_VSI_PB1 HDMIRX_REG(0x03ec)
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#define HDMI_RX_PDEC_VSI_PB2 HDMIRX_REG(0x03f0)
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#define HDMI_RX_PDEC_VSI_PB3 HDMIRX_REG(0x03f4)
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#define HDMI_RX_PDEC_VSI_PB4 HDMIRX_REG(0x03f8)
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#define HDMI_RX_PDEC_VSI_PB5 HDMIRX_REG(0x03fc)
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#define HDMI_RX_CEAVID_CONFIG HDMIRX_REG(0x0400)
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#define HDMI_RX_CEAVID_3DCONFIG HDMIRX_REG(0x0404)
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#define HDMI_RX_CEAVID_HCONFIG_LO HDMIRX_REG(0x0408)
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#define HDMI_RX_CEAVID_HCONFIG_HI HDMIRX_REG(0x040c)
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#define HDMI_RX_CEAVID_VCONFIG_LO HDMIRX_REG(0x0410)
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#define HDMI_RX_CEAVID_VCONFIG_HI HDMIRX_REG(0x0414)
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#define HDMI_RX_CEAVID_STATUS HDMIRX_REG(0x0418)
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#define HDMI_RX_PDEC_AMP_HB HDMIRX_REG(0x0480)
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#define HDMI_RX_PDEC_AMP_PAYLOAD0 HDMIRX_REG(0x0484)
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#define HDMI_RX_PDEC_AMP_PAYLOAD1 HDMIRX_REG(0x0488)
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#define HDMI_RX_PDEC_AMP_PAYLOAD2 HDMIRX_REG(0x048c)
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#define HDMI_RX_PDEC_AMP_PAYLOAD3 HDMIRX_REG(0x0490)
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#define HDMI_RX_PDEC_AMP_PAYLOAD4 HDMIRX_REG(0x0494)
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#define HDMI_RX_PDEC_AMP_PAYLOAD5 HDMIRX_REG(0x0498)
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#define HDMI_RX_PDEC_AMP_PAYLOAD6 HDMIRX_REG(0x049c)
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#define HDMI_RX_PDEC_NTSCVBI_HB HDMIRX_REG(0x04a0)
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#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD0 HDMIRX_REG(0x04a4)
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#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD1 HDMIRX_REG(0x04a8)
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#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD2 HDMIRX_REG(0x04ac)
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#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD3 HDMIRX_REG(0x04b0)
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#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD4 HDMIRX_REG(0x04b4)
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#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD5 HDMIRX_REG(0x04b8)
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#define HDMI_RX_PDEC_NTSCVBI_PAYLOAD6 HDMIRX_REG(0x04bc)
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#define HDMI_RX_PDEC_DRM_HB HDMIRX_REG(0x04c0)
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#define HDMI_RX_PDEC_DRM_PAYLOAD0 HDMIRX_REG(0x04c4)
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#define HDMI_RX_PDEC_DRM_PAYLOAD1 HDMIRX_REG(0x04c8)
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#define HDMI_RX_PDEC_DRM_PAYLOAD2 HDMIRX_REG(0x04cc)
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#define HDMI_RX_PDEC_DRM_PAYLOAD3 HDMIRX_REG(0x04d0)
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#define HDMI_RX_PDEC_DRM_PAYLOAD4 HDMIRX_REG(0x04d4)
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#define HDMI_RX_PDEC_DRM_PAYLOAD5 HDMIRX_REG(0x04d8)
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#define HDMI_RX_PDEC_DRM_PAYLOAD6 HDMIRX_REG(0x04dc)
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#define HDMI_RX_MHLMODE_CTRL HDMIRX_REG(0x0500)
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#define HDMI_RX_CDSENSE_STATUS HDMIRX_REG(0x0504)
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#define HDMI_RX_DESERFIFO_CTRL HDMIRX_REG(0x0508)
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#define HDMI_RX_DESER_INTTRSHCTRL HDMIRX_REG(0x050c)
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#define HDMI_RX_DESER_INTCNTCTRL HDMIRX_REG(0x0510)
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#define HDMI_RX_DESER_INTCNT HDMIRX_REG(0x0514)
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#define HDMI_RX_HDCP_RPT_CTRL HDMIRX_REG(0x0600)
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#define HDMI_RX_HDCP_RPT_BSTATUS HDMIRX_REG(0x0604)
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#define HDMI_RX_HDCP_RPT_KSVFIFO_CTRL HDMIRX_REG(0x0608)
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#define HDMI_RX_HDCP_RPT_KSVFIFO1 HDMIRX_REG(0x060c)
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#define HDMI_RX_HDCP_RPT_KSVFIFO0 HDMIRX_REG(0x0610)
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#define HDMI_RX_HDMI20_CONTROL HDMIRX_REG(0x0800)
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#define HDMI_RX_SCDC_I2CCONFIG HDMIRX_REG(0x0804)
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#define I2CSPIKESUPPR_MASK GENMASK(25, 24)
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#define I2CSPIKESUPPR(x) UPDATE(x, 25, 24)
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#define HDMI_RX_SCDC_CONFIG HDMIRX_REG(0x0808)
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#define HDMI_RX_CHLOCK_CONFIG HDMIRX_REG(0x080c)
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#define CHLOCKMAXER_MASK GENMASK(29, 20)
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#define CHLOCKMAXER(x) UPDATE(x, 29, 20)
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#define MILISECTIMERLIMIT_MASK GENMASK(15, 0)
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#define MILISECTIMERLIMIT(x) UPDATE(x, 15, 0)
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#define HDMI_RX_HDCP22_CONTROL HDMIRX_REG(0x081c)
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#define HDMI_RX_SCDC_REGS0 HDMIRX_REG(0x0820)
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#define HDMI_RX_SCDC_REGS1 HDMIRX_REG(0x0824)
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#define HDMI_RX_SCDC_REGS2 HDMIRX_REG(0x0828)
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#define HDMI_RX_SCDC_REGS3 HDMIRX_REG(0x082c)
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#define HDMI_RX_SCDC_MANSPEC0 HDMIRX_REG(0x0840)
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#define HDMI_RX_SCDC_MANSPEC1 HDMIRX_REG(0x0844)
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#define HDMI_RX_SCDC_MANSPEC2 HDMIRX_REG(0x0848)
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#define HDMI_RX_SCDC_MANSPEC3 HDMIRX_REG(0x084c)
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#define HDMI_RX_SCDC_MANSPEC4 HDMIRX_REG(0x0850)
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#define HDMI_RX_SCDC_WRDATA0 HDMIRX_REG(0x0860)
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#define MANUFACTUREROUI_MASK GENMASK(31, 8)
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#define MANUFACTUREROUI(x) UPDATE(x, 31, 8)
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#define SINKVERSION_MASK GENMASK(7, 0)
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#define SINKVERSION(x) UPDATE(x, 7, 0)
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#define HDMI_RX_SCDC_WRDATA1 HDMIRX_REG(0x0864)
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#define HDMI_RX_SCDC_WRDATA2 HDMIRX_REG(0x0868)
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#define HDMI_RX_SCDC_WRDATA3 HDMIRX_REG(0x086c)
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#define HDMI_RX_SCDC_WRDATA4 HDMIRX_REG(0x0870)
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#define HDMI_RX_SCDC_WRDATA5 HDMIRX_REG(0x0874)
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#define HDMI_RX_SCDC_WRDATA6 HDMIRX_REG(0x0878)
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#define HDMI_RX_SCDC_WRDATA7 HDMIRX_REG(0x087c)
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#define HDMI_RX_HDMI20_STATUS HDMIRX_REG(0x08e0)
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#define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_IN HDMIRX_REG(0x08e8)
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#define HDMI_RX_HDCP2_ESM_GLOBAL_GPIO_OUT HDMIRX_REG(0x08ec)
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#define HDMI_RX_HDCP2_ESM_P0_GPIO_IN HDMIRX_REG(0x08f0)
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#define HDMI_RX_HDCP2_ESM_P0_GPIO_OUT HDMIRX_REG(0x08f4)
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#define HDMI_RX_HDCP22_STATUS HDMIRX_REG(0x08fc)
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#define HDMI_RX_HDMI2_IEN_CLR HDMIRX_REG(0x0f60)
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#define HDMI_RX_HDMI2_IEN_SET HDMIRX_REG(0x0f64)
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#define HDMI_RX_HDMI2_ISTS HDMIRX_REG(0x0f68)
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#define HDMI_RX_HDMI2_IEN HDMIRX_REG(0x0f6c)
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#define HDMI_RX_HDMI2_ICLR HDMIRX_REG(0x0f70)
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#define HDMI_RX_HDMI2_ISET HDMIRX_REG(0x0f74)
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#define HDMI_RX_PDEC_IEN_CLR HDMIRX_REG(0x0f78)
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#define HDMI_RX_PDEC_IEN_SET HDMIRX_REG(0x0f7c)
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#define ACR_N_CHG_IEN BIT(23)
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#define ACR_CTS_CHG_IEN BIT(22)
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#define GCP_AV_MUTE_CHG_ENSET BIT(21)
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#define AIF_RCV_ENSET BIT(19)
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#define AVI_RCV_ENSET BIT(18)
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#define GCP_RCV_ENSET BIT(16)
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#define AMP_RCV_ENSET BIT(14)
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#define HDMI_RX_PDEC_ISTS HDMIRX_REG(0x0f80)
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#define AVI_RCV_ISTS BIT(18)
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#define HDMI_RX_PDEC_IEN HDMIRX_REG(0x0f84)
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#define HDMI_RX_PDEC_ICLR HDMIRX_REG(0x0f88)
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#define AVI_RCV_ICLR BIT(18)
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#define HDMI_RX_PDEC_ISET HDMIRX_REG(0x0f8c)
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#define HDMI_RX_AUD_CEC_IEN_CLR HDMIRX_REG(0x0f90)
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#define HDMI_RX_AUD_CEC_IEN_SET HDMIRX_REG(0x0f94)
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#define HDMI_RX_AUD_CEC_ISTS HDMIRX_REG(0x0f98)
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#define HDMI_RX_AUD_CEC_IEN HDMIRX_REG(0x0f9c)
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#define HDMI_RX_AUD_CEC_ICLR HDMIRX_REG(0x0fa0)
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#define HDMI_RX_AUD_CEC_ISET HDMIRX_REG(0x0fa4)
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#define HDMI_RX_AUD_FIFO_IEN_CLR HDMIRX_REG(0x0fa8)
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#define HDMI_RX_AUD_FIFO_IEN_SET HDMIRX_REG(0x0fac)
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#define HDMI_RX_AUD_FIFO_ISTS HDMIRX_REG(0x0fb0)
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#define HDMI_RX_AUD_FIFO_IEN HDMIRX_REG(0x0fb4)
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#define HDMI_RX_AUD_FIFO_ICLR HDMIRX_REG(0x0fb8)
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#define HDMI_RX_AUD_FIFO_ISET HDMIRX_REG(0x0fbc)
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#define HDMI_RX_MD_IEN_CLR HDMIRX_REG(0x0fc0)
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#define HDMI_RX_MD_IEN_SET HDMIRX_REG(0x0fc4)
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#define VACT_LIN_ENSET BIT(9)
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#define HACT_PIX_ENSET BIT(6)
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#define HS_CLK_ENSET BIT(5)
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#define DE_ACTIVITY_ENSET BIT(2)
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#define VS_ACT_ENSET BIT(1)
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#define HS_ACT_ENSET BIT(0)
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#define HDMI_RX_MD_ISTS HDMIRX_REG(0x0fc8)
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#define HDMI_RX_MD_IEN HDMIRX_REG(0x0fcc)
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#define HDMI_RX_MD_ICLR HDMIRX_REG(0x0fd0)
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#define HDMI_RX_MD_ISET HDMIRX_REG(0x0fd4)
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#define HDMI_RX_HDMI_IEN_CLR HDMIRX_REG(0x0fd8)
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#define HDMI_RX_HDMI_IEN_SET HDMIRX_REG(0x0fdc)
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#define HDCP_DKSET_DONE_ENCLR_MASK BIT(31)
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#define HDCP_DKSET_DONE_ENCLR(x) UPDATE(x, 31, 31)
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#define HDMI_RX_HDMI_ISTS HDMIRX_REG(0x0fe0)
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#define HDMI_RX_HDMI_IEN HDMIRX_REG(0x0fe4)
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#define HDMI_RX_HDMI_ICLR HDMIRX_REG(0x0fe8)
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#define HDMI_RX_HDMI_ISET HDMIRX_REG(0x0fec)
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#define HDMI_RX_DMI_SW_RST HDMIRX_REG(0x0ff0)
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#define HDMI_RX_DMI_DISABLE_IF HDMIRX_REG(0x0ff4)
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#define MAIN_ENABLE BIT(0)
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#define MODET_ENABLE BIT(1)
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#define HDMI_ENABLE BIT(2)
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#define BUS_ENABLE BIT(3)
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#define AUD_ENABLE BIT(4)
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#define CEC_ENABLE BIT(5)
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#define PIXEL_ENABLE BIT(6)
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#define VID_ENABLE_MASK BIT(7)
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#define VID_ENABLE(x) UPDATE(x, 7, 7)
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#define TMDS_ENABLE_MASK BIT(16)
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#define TMDS_ENABLE(x) UPDATE(x, 16, 16)
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#define HDMI_RX_DMI_MODULE_ID_EXT HDMIRX_REG(0x0ff8)
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#define HDMI_RX_DMI_MODULE_ID HDMIRX_REG(0x0ffc)
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#define HDMI_RX_CEC_CTRL HDMIRX_REG(0x1f00)
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#define HDMI_RX_CEC_MASK HDMIRX_REG(0x1f08)
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#define HDMI_RX_CEC_ADDR_L HDMIRX_REG(0x1f14)
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#define HDMI_RX_CEC_ADDR_H HDMIRX_REG(0x1f18)
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#define HDMI_RX_CEC_TX_CNT HDMIRX_REG(0x1f1c)
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#define HDMI_RX_CEC_RX_CNT HDMIRX_REG(0x1f20)
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#define HDMI_RX_CEC_TX_DATA_0 HDMIRX_REG(0x1f40)
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#define HDMI_RX_CEC_TX_DATA_1 HDMIRX_REG(0x1f44)
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#define HDMI_RX_CEC_TX_DATA_2 HDMIRX_REG(0x1f48)
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#define HDMI_RX_CEC_TX_DATA_3 HDMIRX_REG(0x1f4c)
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#define HDMI_RX_CEC_TX_DATA_4 HDMIRX_REG(0x1f50)
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#define HDMI_RX_CEC_TX_DATA_5 HDMIRX_REG(0x1f54)
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#define HDMI_RX_CEC_TX_DATA_6 HDMIRX_REG(0x1f58)
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#define HDMI_RX_CEC_TX_DATA_7 HDMIRX_REG(0x1f5c)
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#define HDMI_RX_CEC_TX_DATA_8 HDMIRX_REG(0x1f60)
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#define HDMI_RX_CEC_TX_DATA_9 HDMIRX_REG(0x1f64)
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#define HDMI_RX_CEC_TX_DATA_10 HDMIRX_REG(0x1f68)
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#define HDMI_RX_CEC_TX_DATA_11 HDMIRX_REG(0x1f6c)
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#define HDMI_RX_CEC_TX_DATA_12 HDMIRX_REG(0x1f70)
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#define HDMI_RX_CEC_TX_DATA_13 HDMIRX_REG(0x1f74)
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#define HDMI_RX_CEC_TX_DATA_14 HDMIRX_REG(0x1f78)
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#define HDMI_RX_CEC_TX_DATA_15 HDMIRX_REG(0x1f7c)
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#define HDMI_RX_CEC_RX_DATA_0 HDMIRX_REG(0x1f80)
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#define HDMI_RX_CEC_RX_DATA_1 HDMIRX_REG(0x1f84)
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#define HDMI_RX_CEC_RX_DATA_2 HDMIRX_REG(0x1f88)
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#define HDMI_RX_CEC_RX_DATA_3 HDMIRX_REG(0x1f8c)
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#define HDMI_RX_CEC_RX_DATA_4 HDMIRX_REG(0x1f90)
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#define HDMI_RX_CEC_RX_DATA_5 HDMIRX_REG(0x1f94)
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#define HDMI_RX_CEC_RX_DATA_6 HDMIRX_REG(0x1f98)
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#define HDMI_RX_CEC_RX_DATA_7 HDMIRX_REG(0x1f9c)
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#define HDMI_RX_CEC_RX_DATA_8 HDMIRX_REG(0x1fa0)
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#define HDMI_RX_CEC_RX_DATA_9 HDMIRX_REG(0x1fa4)
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#define HDMI_RX_CEC_RX_DATA_10 HDMIRX_REG(0x1fa8)
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#define HDMI_RX_CEC_RX_DATA_11 HDMIRX_REG(0x1fac)
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#define HDMI_RX_CEC_RX_DATA_12 HDMIRX_REG(0x1fb0)
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#define HDMI_RX_CEC_RX_DATA_13 HDMIRX_REG(0x1fb4)
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#define HDMI_RX_CEC_RX_DATA_14 HDMIRX_REG(0x1fb8)
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#define HDMI_RX_CEC_RX_DATA_15 HDMIRX_REG(0x1fbc)
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#define HDMI_RX_CEC_LOCK HDMIRX_REG(0x1fc0)
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#define HDMI_RX_CEC_WAKEUPCTRL HDMIRX_REG(0x1fc4)
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#define HDMI_RX_CBUSSWRESETREQ HDMIRX_REG(0x3000)
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#define HDMI_RX_CBUSENABLEIF HDMIRX_REG(0x3004)
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#define HDMI_RX_CB_LOCKONCLOCK_STS HDMIRX_REG(0x3010)
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#define HDMI_RX_CB_LOCKONCLOCKCLR HDMIRX_REG(0x3014)
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#define HDMI_RX_CBUSIOCTRL HDMIRX_REG(0x3020)
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#define HDMI_RX_DD_CTRL HDMIRX_REG(0x3040)
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#define HDMI_RX_DD_OP_CTRL HDMIRX_REG(0x3044)
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#define HDMI_RX_DD_STS HDMIRX_REG(0x3048)
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#define HDMI_RX_DD_BYPASS_EN HDMIRX_REG(0x304c)
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#define HDMI_RX_DD_BYPASS_CTRL HDMIRX_REG(0x3050)
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#define HDMI_RX_DD_BYPASS_CBUS HDMIRX_REG(0x3054)
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#define HDMI_RX_LL_TXPCKFIFO HDMIRX_REG(0x3080)
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#define HDMI_RX_LL_RXPCKFIFO_RD_CLR HDMIRX_REG(0x3084)
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#define HDMI_RX_LL_RXPCKFIFO_A HDMIRX_REG(0x3088)
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#define HDMI_RX_LL_RXPCKFIFO_B HDMIRX_REG(0x308c)
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#define HDMI_RX_LL_TXPCKCTRL_0 HDMIRX_REG(0x3090)
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#define HDMI_RX_LL_TXPCKCTRL_1 HDMIRX_REG(0x3094)
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#define HDMI_RX_LL_PCKFIFO_STS HDMIRX_REG(0x309c)
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#define HDMI_RX_LL_RXPCKCTRL_0 HDMIRX_REG(0x30a0)
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#define HDMI_RX_LL_RXPCKCTRL_1 HDMIRX_REG(0x30a4)
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#define HDMI_RX_LL_INTTRSHLDCTRL HDMIRX_REG(0x30b0)
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#define HDMI_RX_LL_INTCNTCTRL HDMIRX_REG(0x30b4)
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#define HDMI_RX_LL_INTCNT_0 HDMIRX_REG(0x30b8)
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#define HDMI_RX_LL_INTCNT_1 HDMIRX_REG(0x30bc)
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#define HDMI_RX_CBHDCP_OPCTRL HDMIRX_REG(0x3100)
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#define HDMI_RX_CBHDCP_WDATA_0 HDMIRX_REG(0x3104)
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#define HDMI_RX_CBHDCP_WDATA_1 HDMIRX_REG(0x3108)
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#define HDMI_RX_CBHDCP_RDATA_0 HDMIRX_REG(0x310c)
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#define HDMI_RX_CBHDCP_RDATA_1 HDMIRX_REG(0x3110)
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#define HDMI_RX_CBHDCP_STATUS HDMIRX_REG(0x3114)
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#define HDMI_RX_CBHDCP_DDC_REPORT HDMIRX_REG(0x3118)
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#define HDMI_RX_ISTAT_CB_DD HDMIRX_REG(0x3200)
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#define HDMI_RX_IMASK_CB_DD HDMIRX_REG(0x3204)
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#define HDMI_RX_IFORCE_CB_DD HDMIRX_REG(0x3208)
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#define HDMI_RX_ICLEAR_CB_DD HDMIRX_REG(0x320c)
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#define HDMI_RX_IMUTE_CB_DD HDMIRX_REG(0x3210)
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#define HDMI_RX_ISTAT_CB_LL HDMIRX_REG(0x3220)
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#define HDMI_RX_IMASK_CB_LL HDMIRX_REG(0x3224)
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#define HDMI_RX_IFORCE_CB_LL HDMIRX_REG(0x3228)
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#define HDMI_RX_ICLEAR_CB_LL HDMIRX_REG(0x322c)
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#define HDMI_RX_IMUTE_CB_LL HDMIRX_REG(0x3230)
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#define HDMI_RX_ISTAT_CB_HDCP HDMIRX_REG(0x3240)
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#define HDMI_RX_IMASK_CB_HDCP HDMIRX_REG(0x3244)
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#define HDMI_RX_IFORCE_CB_HDCP HDMIRX_REG(0x3248)
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#define HDMI_RX_ICLEAR_CB_HDCP HDMIRX_REG(0x324c)
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#define HDMI_RX_IMUTE_CB_HDCP HDMIRX_REG(0x3250)
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#define HDMI_RX_ISTAT_CB_MCTRL HDMIRX_REG(0x3260)
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#define HDMI_RX_IMASK_CB_MCTRL HDMIRX_REG(0x3264)
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#define HDMI_RX_IFORCE_CB_MCTRL HDMIRX_REG(0x3268)
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#define HDMI_RX_ICLEAR_CB_MCTRL HDMIRX_REG(0x326c)
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#define HDMI_RX_IMUTE_CB_MCTRL HDMIRX_REG(0x3270)
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#define HDMI_RX_IMASTER_MUTE_CB HDMIRX_REG(0x32e0)
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#define HDMI_RX_IVECTOR_INDEX_CB HDMIRX_REG(0x32e4)
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#define HDMI_RX_MAX_REGISTER HDMI_RX_IVECTOR_INDEX_CB
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#define EDID_NUM_BLOCKS_MAX 2
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#define EDID_BLOCK_SIZE 128
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#define HDMIRX_PLUGIN BIT(0)
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#define HDMIRX_PLUGOUT BIT(1)
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#define HDMIRX_CHANGED BIT(2)
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#define HDMIRX_NOSIGNAL BIT(3)
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#define HDMIRX_NOLOCK BIT(4)
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void rk628_hdmirx_enable_interrupts(struct rk628 *rk628, bool en);
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int rk628_hdmirx_enable(struct rk628 *rk628);
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void rk628_hdmirx_disable(struct rk628 *rk628);
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int rk628_hdmirx_detect(struct rk628 *rk628);
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#endif
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