// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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*
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* Author: Chen Shunqing <csq@rock-chips.com>
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*/
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#include <linux/gpio/consumer.h>
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#include <linux/of_device.h>
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#include "rk628.h"
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#include "rk628_combrxphy.h"
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#include "rk628_config.h"
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#include "rk628_hdmirx.h"
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#define POLL_INTERVAL_MS 1000
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#define MODETCLK_CNT_NUM 1000
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#define MODETCLK_HZ 49500000
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#define RXPHY_CFG_MAX_TIMES 1
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static u8 debug;
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static u8 edid_init_data[] = {
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0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
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0x49, 0x78, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
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0x12, 0x1E, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
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0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
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0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
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0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
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0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
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0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x50,
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0x72, 0x6F, 0x6A, 0x65, 0x63, 0x74, 0x6F, 0x72,
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0x0A, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
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0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x18,
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0x02, 0x03, 0x13, 0x71, 0x40, 0x23, 0x09, 0x07,
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0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C,
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0x00, 0x10, 0x00, 0x02, 0x3A, 0x80, 0x18, 0x71,
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0x38, 0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0x20,
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0xC2, 0x31, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
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};
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struct rk628_hdmi_mode {
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u32 hdisplay;
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u32 hstart;
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u32 hend;
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u32 htotal;
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u32 vdisplay;
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u32 vstart;
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u32 vend;
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u32 vtotal;
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u32 clock;
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unsigned int flags;
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};
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struct rk628_hdmirx {
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bool plugin;
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bool res_change;
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struct rk628_hdmi_mode mode;
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u32 input_format;
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u32 fs_audio;
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bool audio_present;
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bool hpd_output_inverted;
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bool src_mode_4K_yuv420;
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bool phy_lock;
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};
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static void rk628_hdmirx_ctrl_enable(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
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SW_INPUT_MODE_MASK,
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SW_INPUT_MODE(INPUT_MODE_HDMI));
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rk628_i2c_write(rk628, HDMI_RX_HDMI20_CONTROL, 0x10001f10);
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rk628_i2c_write(rk628, HDMI_RX_HDMI_MODE_RECOVER, 0x00000021);
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rk628_i2c_write(rk628, HDMI_RX_PDEC_CTRL, 0xbfff8011);
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rk628_i2c_write(rk628, HDMI_RX_PDEC_ASP_CTRL, 0x00000040);
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rk628_i2c_write(rk628, HDMI_RX_HDMI_RESMPL_CTRL, 0x00000001);
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rk628_i2c_write(rk628, HDMI_RX_HDMI_SYNC_CTRL, 0x00000014);
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rk628_i2c_write(rk628, HDMI_RX_PDEC_ERR_FILTER, 0x00000008);
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rk628_i2c_write(rk628, HDMI_RX_SCDC_I2CCONFIG, 0x01000000);
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rk628_i2c_write(rk628, HDMI_RX_SCDC_CONFIG, 0x00000001);
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rk628_i2c_write(rk628, HDMI_RX_SCDC_WRDATA0, 0xabcdef01);
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rk628_i2c_write(rk628, HDMI_RX_CHLOCK_CONFIG, 0x0030c15c);
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rk628_i2c_write(rk628, HDMI_RX_HDMI_ERROR_PROTECT, 0x000d0c98);
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rk628_i2c_write(rk628, HDMI_RX_MD_HCTRL1, 0x00000010);
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rk628_i2c_write(rk628, HDMI_RX_MD_HCTRL2, 0x00001738);
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rk628_i2c_write(rk628, HDMI_RX_MD_VCTRL, 0x00000002);
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rk628_i2c_write(rk628, HDMI_RX_MD_VTH, 0x0000073a);
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rk628_i2c_write(rk628, HDMI_RX_MD_IL_POL, 0x00000004);
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rk628_i2c_write(rk628, HDMI_RX_PDEC_ACRM_CTRL, 0x00000000);
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rk628_i2c_write(rk628, HDMI_RX_HDMI_DCM_CTRL, 0x00040414);
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rk628_i2c_write(rk628, HDMI_RX_HDMI_CKM_EVLTM, 0x00103e70);
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rk628_i2c_write(rk628, HDMI_RX_HDMI_CKM_F, 0x0c1c0b54);
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rk628_i2c_write(rk628, HDMI_RX_HDMI_RESMPL_CTRL, 0x00000001);
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rk628_i2c_update_bits(rk628, HDMI_RX_HDCP_SETTINGS,
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HDMI_RESERVED_MASK |
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FAST_I2C_MASK |
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ONE_DOT_ONE_MASK |
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FAST_REAUTH_MASK,
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HDMI_RESERVED(1) |
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FAST_I2C(0) |
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ONE_DOT_ONE(1) |
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FAST_REAUTH(1));
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}
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static void rk628_hdmirx_video_unmute(struct rk628 *rk628, u8 unmute)
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{
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rk628_i2c_update_bits(rk628, HDMI_RX_DMI_DISABLE_IF, VID_ENABLE_MASK, VID_ENABLE(unmute));
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}
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static void rk628_hdmirx_hpd_ctrl(struct rk628 *rk628, bool en)
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{
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u8 en_level, set_level;
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struct rk628_hdmirx *hdmirx = rk628->hdmirx;
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dev_dbg(rk628->dev, "%s: %sable, hpd invert:%d\n", __func__,
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en ? "en" : "dis", hdmirx->hpd_output_inverted);
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en_level = hdmirx->hpd_output_inverted ? 0 : 1;
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set_level = en ? en_level : !en_level;
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rk628_i2c_update_bits(rk628, HDMI_RX_HDMI_SETUP_CTRL,
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HOT_PLUG_DETECT_MASK, HOT_PLUG_DETECT(set_level));
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}
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static void rk628_hdmirx_disable_edid(struct rk628 *rk628)
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{
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rk628_hdmirx_hpd_ctrl(rk628, false);
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rk628_hdmirx_video_unmute(rk628, 0);
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}
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static void rk628_hdmirx_enable_edid(struct rk628 *rk628)
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{
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rk628_hdmirx_hpd_ctrl(rk628, true);
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}
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static int tx_5v_power_present(struct rk628 *rk628)
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{
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bool ret;
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int val, i, cnt;
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/* Direct Mode */
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if (!rk628->plugin_det_gpio)
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return 1;
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cnt = 0;
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for (i = 0; i < 5; i++) {
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val = gpiod_get_value(rk628->plugin_det_gpio);
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if (val > 0)
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cnt++;
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usleep_range(500, 600);
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}
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ret = (cnt >= 3) ? 1 : 0;
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dev_dbg(rk628->dev, "%s: %d\n", __func__, ret);
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return ret;
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}
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static int rk628_hdmirx_init_edid(struct rk628 *rk628)
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{
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struct rk628_display_mode *src_mode;
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struct rk628_hdmirx *hdmirx = rk628->hdmirx;
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u32 val;
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u8 csum = 0;
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int i, base, j;
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src_mode = rk628_display_get_src_mode(rk628);
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for (j = 0, base = 0x36; j < 2; j++) {
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csum = 0;
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/* clock-frequency */
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edid_init_data[base + 1] = ((src_mode->clock / 10) & 0xff00) >> 8;
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edid_init_data[base] = (src_mode->clock / 10) & 0xff;
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/* hactive low 8 bits */
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edid_init_data[base + 2] = src_mode->hdisplay & 0xff;
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/* hblanking low 8 bits */
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val = src_mode->htotal - src_mode->hdisplay;
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edid_init_data[base + 3] = val & 0xff;
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/* hactive high 4 bits & hblanking low 4 bits */
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edid_init_data[base + 4] =
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((src_mode->hdisplay & 0xf00) >> 4) + ((val & 0xf00) >> 8);
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/* vactive low 8 bits */
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edid_init_data[base + 5] = src_mode->vdisplay & 0xff;
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/* vblanking low 8 bits */
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val = src_mode->vtotal - src_mode->vdisplay;
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edid_init_data[base + 6] = val & 0xff;
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/* vactive high 4 bits & vblanking low 4 bits */
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edid_init_data[base + 7] =
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((src_mode->vdisplay & 0xf00) >> 4) + ((val & 0xf00) >> 8);
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/* hsync pulse offset low 8 bits */
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val = src_mode->hsync_start - src_mode->hdisplay;
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edid_init_data[base + 8] = val & 0xff;
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/* hsync pulse width low 8 bits */
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val = src_mode->hsync_end - src_mode->hsync_start;
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edid_init_data[base + 9] = val & 0xff;
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/* vsync pulse offset low 4 bits & vsync pulse width low 4 bits */
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val = ((src_mode->vsync_start - src_mode->vdisplay) & 0xf) << 4;
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edid_init_data[base + 10] = val;
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edid_init_data[base + 10] += (src_mode->vsync_end - src_mode->vsync_start) & 0xf;
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/* 6~7bits:hsync pulse offset;
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* 4~6bits:hsync pulse width;
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* 2~3bits:vsync pulse offset;
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* 0~1bits:vsync pulse width
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*/
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edid_init_data[base + 11] =
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((src_mode->hsync_start - src_mode->hdisplay) & 0x300) >> 2;
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edid_init_data[base + 11] +=
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((src_mode->hsync_end - src_mode->hsync_start) & 0x700) >> 4;
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edid_init_data[base + 11] +=
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((src_mode->vsync_start - src_mode->vdisplay) & 0x30) >> 2;
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edid_init_data[base + 11] +=
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((src_mode->vsync_end - src_mode->vsync_start) & 0x30) >> 4;
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edid_init_data[base + 17] = 0x18;
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if (src_mode->flags & DRM_MODE_FLAG_PHSYNC)
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edid_init_data[base + 17] |= 0x2;
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if (src_mode->flags & DRM_MODE_FLAG_PVSYNC)
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edid_init_data[base + 17] |= 0x4;
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if (hdmirx->src_mode_4K_yuv420 && src_mode->clock == 594000) {
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edid_init_data[0x80 + 0x2] = 0x16;
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edid_init_data[0x80 + 0x13] = 0xe2;
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edid_init_data[0x80 + 0x14] = 0x0E;
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edid_init_data[0x80 + 0x15] = 0x61;
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base += (0x5d + 0x3);
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} else {
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base += 0x5d;
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}
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for (i = 0; i < 127; i++)
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csum += edid_init_data[i + j * 128];
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edid_init_data[127 + j * 128] = (u8)0 - csum;
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}
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return 0;
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}
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static int rk628_hdmirx_set_edid(struct rk628 *rk628)
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{
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int i;
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u32 val;
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u16 edid_len;
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rk628_hdmirx_disable_edid(rk628);
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if (!rk628->plugin_det_gpio)
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return 0;
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/* edid access by apb when write, i2c slave addr: 0x0 */
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
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SW_ADAPTER_I2CSLADR_MASK |
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SW_EDID_MODE_MASK,
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SW_ADAPTER_I2CSLADR(0) |
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SW_EDID_MODE(1));
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rk628_hdmirx_init_edid(rk628);
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edid_len = ARRAY_SIZE(edid_init_data);
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for (i = 0; i < edid_len; i++)
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rk628_i2c_write(rk628, EDID_BASE + i * 4, edid_init_data[i]);
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/* read out for debug */
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if (debug >= 3) {
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pr_info("====== Read EDID: ======\n");
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for (i = 0; i < edid_len; i++) {
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rk628_i2c_read(rk628, EDID_BASE + i * 4, &val);
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pr_info("0x%02x ", val);
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if ((i + 1) % 8 == 0)
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pr_info("\n");
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}
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pr_info("============\n");
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}
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/* edid access by RX's i2c, i2c slave addr: 0x0 */
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
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SW_ADAPTER_I2CSLADR_MASK |
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SW_EDID_MODE_MASK,
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SW_ADAPTER_I2CSLADR(0) |
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SW_EDID_MODE(0));
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mdelay(1);
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return 0;
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}
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static int rk628_hdmirx_phy_power_on(struct rk628 *rk628, int f)
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{
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int ret;
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bool rxphy_pwron = false;
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if (rxphy_pwron) {
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dev_info(rk628->dev, "rxphy already power on, power off!\n");
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ret = rk628_combrxphy_power_off(rk628);
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if (ret)
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dev_info(rk628->dev, "hdmi rxphy power off failed!\n");
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else
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rxphy_pwron = false;
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}
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udelay(1000);
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if (rxphy_pwron == false) {
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ret = rk628_combrxphy_power_on(rk628, f);
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if (ret) {
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rxphy_pwron = false;
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dev_info(rk628->dev, "hdmi rxphy power on failed\n");
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} else {
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rxphy_pwron = true;
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dev_info(rk628->dev, "hdmi rxphy power on success\n");
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}
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}
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dev_info(rk628->dev, "%s:rxphy_pwron=%d\n", __func__, rxphy_pwron);
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return ret;
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}
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static void rk628_hdmirx_get_timing(struct rk628 *rk628)
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{
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u32 hact, vact, htotal, vtotal, fps, status;
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u32 val;
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u32 modetclk_cnt_hs, modetclk_cnt_vs, hs, vs;
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u32 hofs_pix, hbp, hfp, vbp, vfp;
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u32 tmds_clk, tmdsclk_cnt;
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u64 tmp_data;
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u32 interlaced;
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u32 hfrontporch, hsync, hbackporch, vfrontporch, vsync, vbackporch;
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unsigned long long pixelclock;
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unsigned long flags = 0;
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struct rk628_hdmirx *hdmirx = rk628->hdmirx;
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rk628_i2c_read(rk628, HDMI_RX_SCDC_REGS1, &val);
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status = val;
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rk628_i2c_read(rk628, HDMI_RX_MD_STS, &val);
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interlaced = val & ILACE_STS ? 1 : 0;
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rk628_i2c_read(rk628, HDMI_RX_MD_HACT_PX, &val);
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hact = val & 0xffff;
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rk628_i2c_read(rk628, HDMI_RX_MD_VAL, &val);
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vact = val & 0xffff;
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rk628_i2c_read(rk628, HDMI_RX_MD_HT1, &val);
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htotal = (val >> 16) & 0xffff;
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rk628_i2c_read(rk628, HDMI_RX_MD_VTL, &val);
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vtotal = val & 0xffff;
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rk628_i2c_read(rk628, HDMI_RX_MD_HT1, &val);
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hofs_pix = val & 0xffff;
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rk628_i2c_read(rk628, HDMI_RX_MD_VOL, &val);
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vbp = (val & 0xffff) + 1;
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rk628_i2c_read(rk628, HDMI_RX_HDMI_CKM_RESULT, &val);
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tmdsclk_cnt = val & 0xffff;
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tmp_data = tmdsclk_cnt;
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tmp_data = ((tmp_data * MODETCLK_HZ) + MODETCLK_CNT_NUM / 2);
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do_div(tmp_data, MODETCLK_CNT_NUM);
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tmds_clk = tmp_data;
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if (!(htotal && vtotal)) {
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dev_info(rk628->dev, "timing err, htotal:%d, vtotal:%d\n", htotal, vtotal);
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return;
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}
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fps = (tmds_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
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rk628_i2c_read(rk628, HDMI_RX_MD_HT0, &val);
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modetclk_cnt_hs = val & 0xffff;
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hs = (tmdsclk_cnt * modetclk_cnt_hs + MODETCLK_CNT_NUM / 2) /
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MODETCLK_CNT_NUM;
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rk628_i2c_read(rk628, HDMI_RX_MD_VSC, &val);
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modetclk_cnt_vs = val & 0xffff;
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vs = (tmdsclk_cnt * modetclk_cnt_vs + MODETCLK_CNT_NUM / 2) /
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MODETCLK_CNT_NUM;
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vs = (vs + htotal / 2) / htotal;
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rk628_i2c_read(rk628, HDMI_RX_HDMI_STS, &val);
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if (val & BIT(8))
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flags |= DRM_MODE_FLAG_PHSYNC;
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else
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flags |= DRM_MODE_FLAG_NHSYNC;
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if (val & BIT(9))
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flags |= DRM_MODE_FLAG_PVSYNC;
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else
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flags |= DRM_MODE_FLAG_NVSYNC;
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if ((hofs_pix < hs) || (htotal < (hact + hofs_pix)) ||
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(vtotal < (vact + vs + vbp))) {
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dev_info(rk628->dev,
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"timing err, total:%dx%d, act:%dx%d, hofs:%d, hs:%d, vs:%d, vbp:%d\n",
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htotal, vtotal, hact, vact, hofs_pix, hs, vs, vbp);
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return;
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}
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hbp = hofs_pix - hs;
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hfp = htotal - hact - hofs_pix;
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vfp = vtotal - vact - vs - vbp;
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dev_info(rk628->dev, "cnt_num:%d, tmds_cnt:%d, hs_cnt:%d, vs_cnt:%d, hofs:%d\n",
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MODETCLK_CNT_NUM, tmdsclk_cnt, modetclk_cnt_hs, modetclk_cnt_vs, hofs_pix);
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hfrontporch = hfp;
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hsync = hs;
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hbackporch = hbp;
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vfrontporch = vfp;
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vsync = vs;
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vbackporch = vbp;
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pixelclock = htotal * vtotal * fps;
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|
if (interlaced == 1) {
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vsync = vsync + 1;
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pixelclock /= 2;
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}
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hdmirx->mode.clock = pixelclock / 1000;
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hdmirx->mode.hdisplay = hact;
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hdmirx->mode.hstart = hdmirx->mode.hdisplay + hfrontporch;
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hdmirx->mode.hend = hdmirx->mode.hstart + hsync;
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hdmirx->mode.htotal = hdmirx->mode.hend + hbackporch;
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hdmirx->mode.vdisplay = vact;
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hdmirx->mode.vstart = hdmirx->mode.vdisplay + vfrontporch;
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hdmirx->mode.vend = hdmirx->mode.vstart + vsync;
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hdmirx->mode.vtotal = hdmirx->mode.vend + vbackporch;
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hdmirx->mode.flags = flags;
|
|
dev_info(rk628->dev, "SCDC_REGS1:%#x, act:%dx%d, total:%dx%d, fps:%d, pixclk:%llu\n",
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status, hact, vact, htotal, vtotal, fps, pixelclock);
|
dev_info(rk628->dev, "hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d, interlace:%d\n",
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hfrontporch, hsync, hbackporch, vfrontporch, vsync, vbackporch, interlaced);
|
}
|
|
static int rk628_hdmirx_phy_setup(struct rk628 *rk628)
|
{
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u32 i, cnt, val;
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u32 width, height, frame_width, frame_height, status;
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struct rk628_display_mode *src_mode;
|
struct rk628_hdmirx *hdmirx = rk628->hdmirx;
|
int f;
|
struct rk628_display_mode *dst_mode;
|
|
/* Bit31 is used to distinguish HDMI cable mode and direct connection
|
* mode in the rk628_combrxphy driver.
|
* Bit31: 0 -direct connection mode;
|
* 1 -cable mode;
|
* The cable mode is to know the input clock frequency through cdr_mode
|
* in the rk628_combrxphy driver, and the cable mode supports up to
|
* 297M, so 297M is passed uniformly here.
|
*/
|
f = (297000 | BIT(31));
|
dst_mode = rk628_display_get_dst_mode(rk628);
|
/*
|
* force 594m mode to yuv420 format.
|
* bit30 is used to indicate whether it is yuv420 format.
|
*/
|
if (hdmirx->src_mode_4K_yuv420 && dst_mode->clock == 594000)
|
f |= BIT(30);
|
|
for (i = 0; i < RXPHY_CFG_MAX_TIMES; i++) {
|
rk628_hdmirx_phy_power_on(rk628, f);
|
cnt = 0;
|
|
do {
|
cnt++;
|
udelay(2000);
|
rk628_i2c_read(rk628, HDMI_RX_MD_HACT_PX, &val);
|
width = val & 0xffff;
|
rk628_i2c_read(rk628, HDMI_RX_MD_HT1, &val);
|
frame_width = (val >> 16) & 0xffff;
|
|
rk628_i2c_read(rk628, HDMI_RX_MD_VAL, &val);
|
height = val & 0xffff;
|
rk628_i2c_read(rk628, HDMI_RX_MD_VTL, &val);
|
frame_height = val & 0xffff;
|
|
rk628_i2c_read(rk628, HDMI_RX_SCDC_REGS1, &val);
|
status = val;
|
|
dev_info(rk628->dev,
|
"%s read wxh:%dx%d, total:%dx%d, SCDC_REGS1:%#x, cnt:%d\n",
|
__func__, width, height, frame_width,
|
frame_height, status, cnt);
|
|
if (cnt >= 15)
|
break;
|
} while ((status & 0xfff) != 0xf00);
|
|
if ((status & 0xfff) != 0xf00) {
|
dev_info(rk628->dev, "%s hdmi rxphy lock failed, retry:%d\n",
|
__func__, i);
|
continue;
|
} else {
|
rk628_hdmirx_get_timing(rk628);
|
|
src_mode = rk628_display_get_src_mode(rk628);
|
src_mode->clock = hdmirx->mode.clock;
|
src_mode->hdisplay = hdmirx->mode.hdisplay;
|
src_mode->hsync_start = hdmirx->mode.hstart;
|
src_mode->hsync_end = hdmirx->mode.hend;
|
src_mode->htotal = hdmirx->mode.htotal;
|
|
src_mode->vdisplay = hdmirx->mode.vdisplay;
|
src_mode->vsync_start = hdmirx->mode.vstart;
|
src_mode->vsync_end = hdmirx->mode.vend;
|
src_mode->vtotal = hdmirx->mode.vtotal;
|
src_mode->flags = hdmirx->mode.flags;
|
if (hdmirx->src_mode_4K_yuv420 && dst_mode->clock == 594000) {
|
rk628_mode_copy(src_mode, dst_mode);
|
src_mode->flags = DRM_MODE_FLAG_PHSYNC|DRM_MODE_FLAG_PVSYNC;
|
}
|
|
break;
|
}
|
}
|
|
if (i == RXPHY_CFG_MAX_TIMES) {
|
hdmirx->phy_lock = false;
|
return -1;
|
}
|
hdmirx->phy_lock = true;
|
|
return 0;
|
}
|
|
static u32 rk628_hdmirx_get_input_format(struct rk628 *rk628)
|
{
|
u32 val, format, avi_pb = 0;
|
u8 i;
|
u8 cnt = 0, max_cnt = 2;
|
struct rk628_hdmirx *hdmirx = rk628->hdmirx;
|
|
rk628_i2c_read(rk628, HDMI_RX_PDEC_ISTS, &val);
|
if (val & AVI_RCV_ISTS) {
|
for (i = 0; i < 100; i++) {
|
rk628_i2c_read(rk628, HDMI_RX_PDEC_AVI_PB, &format);
|
dev_dbg(rk628->dev, "%s PDEC_AVI_PB:%#x\n", __func__, format);
|
if (format && format == avi_pb) {
|
if (++cnt >= max_cnt)
|
break;
|
} else {
|
cnt = 0;
|
avi_pb = format;
|
}
|
msleep(30);
|
}
|
format = (avi_pb & VIDEO_FORMAT) >> 5;
|
switch (format) {
|
case 0:
|
hdmirx->input_format = BUS_FMT_RGB;
|
break;
|
case 1:
|
hdmirx->input_format = BUS_FMT_YUV422;
|
break;
|
case 2:
|
hdmirx->input_format = BUS_FMT_YUV444;
|
break;
|
case 3:
|
hdmirx->input_format = BUS_FMT_YUV420;
|
break;
|
default:
|
hdmirx->input_format = BUS_FMT_RGB;
|
break;
|
}
|
rk628_i2c_write(rk628, HDMI_RX_PDEC_ICLR, AVI_RCV_ISTS);
|
}
|
|
return hdmirx->input_format;
|
}
|
|
static int rk628_check_signal(struct rk628 *rk628)
|
{
|
u32 hact, vact, val;
|
|
rk628_i2c_read(rk628, HDMI_RX_MD_HACT_PX, &val);
|
hact = val & 0xffff;
|
rk628_i2c_read(rk628, HDMI_RX_MD_VAL, &val);
|
vact = val & 0xffff;
|
|
if (!hact || !vact) {
|
dev_info(rk628->dev, "no signal\n");
|
return 0;
|
}
|
|
return 1;
|
}
|
|
static bool rk628_hdmirx_status_change(struct rk628 *rk628)
|
{
|
u32 hact, vact, val;
|
struct rk628_hdmirx *hdmirx = rk628->hdmirx;
|
|
rk628_i2c_read(rk628, HDMI_RX_MD_HACT_PX, &val);
|
hact = val & 0xffff;
|
rk628_i2c_read(rk628, HDMI_RX_MD_VAL, &val);
|
vact = val & 0xffff;
|
if (!rk628->plugin_det_gpio && !hact && !vact)
|
return true;
|
|
if (hact != hdmirx->mode.hdisplay || vact != hdmirx->mode.vdisplay) {
|
dev_info(rk628->dev, "new: hdisplay=%d, vdisplay=%d\n", hact, vact);
|
dev_info(rk628->dev, "old: hdisplay=%d, vdisplay=%d\n",
|
hdmirx->mode.hdisplay, hdmirx->mode.vdisplay);
|
return true;
|
}
|
|
rk628_hdmirx_get_input_format(rk628);
|
if (hdmirx->input_format != rk628_get_input_bus_format(rk628))
|
return true;
|
|
return false;
|
}
|
|
static int rk628_hdmirx_init(struct rk628 *rk628)
|
{
|
struct rk628_hdmirx *hdmirx;
|
struct device *dev = rk628->dev;
|
|
hdmirx = devm_kzalloc(rk628->dev, sizeof(*hdmirx), GFP_KERNEL);
|
if (!hdmirx)
|
return -ENOMEM;
|
rk628->hdmirx = hdmirx;
|
|
hdmirx->hpd_output_inverted = of_property_read_bool(dev->of_node,
|
"hpd-output-inverted");
|
|
hdmirx->src_mode_4K_yuv420 = of_property_read_bool(dev->of_node,
|
"src-mode-4k-yuv420");
|
|
/* HDMIRX IOMUX */
|
rk628_i2c_write(rk628, GRF_GPIO1AB_SEL_CON, HIWORD_UPDATE(0x7, 10, 8));
|
//i2s pinctrl
|
rk628_i2c_write(rk628, GRF_GPIO0AB_SEL_CON, 0x155c155c);
|
|
/* if GVI and HDMITX OUT, HDMIRX missing signal */
|
rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
|
SW_OUTPUT_MODE_MASK, SW_OUTPUT_MODE(OUTPUT_MODE_RGB));
|
rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
|
SW_INPUT_MODE_MASK, SW_INPUT_MODE(INPUT_MODE_HDMI));
|
rk628_hdmirx_set_edid(rk628);
|
/* clear avi rcv interrupt */
|
rk628_i2c_write(rk628, HDMI_RX_PDEC_ICLR, AVI_RCV_ISTS);
|
|
dev_info(rk628->dev, "hdmirx driver version: %s\n", DRIVER_VERSION);
|
|
return 0;
|
}
|
|
void rk628_hdmirx_enable_interrupts(struct rk628 *rk628, bool en)
|
{
|
u32 pdec_ien, md_ien;
|
u32 md_mask = 0;
|
|
md_mask = VACT_LIN_ENSET | HACT_PIX_ENSET | HS_CLK_ENSET;
|
dev_dbg(rk628->dev, "%s: %sable\n", __func__, en ? "en" : "dis");
|
/* clr irq */
|
rk628_i2c_write(rk628, HDMI_RX_MD_ICLR, md_mask);
|
if (en) {
|
rk628_i2c_write(rk628, HDMI_RX_MD_IEN_SET, md_mask);
|
} else {
|
rk628_i2c_write(rk628, HDMI_RX_MD_IEN_CLR, md_mask);
|
rk628_i2c_write(rk628, HDMI_RX_AUD_FIFO_IEN_CLR, 0x1f);
|
}
|
usleep_range(5000, 5000);
|
rk628_i2c_read(rk628, HDMI_RX_MD_IEN, &md_ien);
|
rk628_i2c_read(rk628, HDMI_RX_PDEC_IEN, &pdec_ien);
|
dev_dbg(rk628->dev, "%s MD_IEN:%#x, PDEC_IEN:%#x\n", __func__, md_ien, pdec_ien);
|
}
|
|
int rk628_hdmirx_enable(struct rk628 *rk628)
|
{
|
int ret;
|
struct rk628_hdmirx *hdmirx;
|
|
if (!rk628->hdmirx) {
|
ret = rk628_hdmirx_init(rk628);
|
if (ret < 0)
|
return HDMIRX_PLUGOUT;
|
}
|
|
hdmirx = rk628->hdmirx;
|
if (tx_5v_power_present(rk628)) {
|
hdmirx->plugin = true;
|
rk628_hdmirx_enable_edid(rk628);
|
rk628_hdmirx_ctrl_enable(rk628);
|
rk628_hdmirx_phy_setup(rk628);
|
rk628_hdmirx_get_input_format(rk628);
|
rk628_set_input_bus_format(rk628, hdmirx->input_format);
|
dev_info(rk628->dev, "hdmirx plug in\n");
|
dev_info(rk628->dev, "input: %d, output: %d\n", hdmirx->input_format,
|
rk628_get_output_bus_format(rk628));
|
if (!rk628_check_signal(rk628))
|
return HDMIRX_PLUGIN | HDMIRX_NOSIGNAL;
|
|
rk628_hdmirx_video_unmute(rk628, 1);
|
return HDMIRX_PLUGIN;
|
}
|
|
hdmirx->plugin = false;
|
rk628_hdmirx_disable_edid(rk628);
|
rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_I2S_DATA_OEN_MASK, SW_I2S_DATA_OEN(1));
|
|
return HDMIRX_PLUGOUT;
|
}
|
|
void rk628_hdmirx_disable(struct rk628 *rk628)
|
{
|
int ret;
|
struct rk628_hdmirx *hdmirx;
|
|
if (!rk628->hdmirx) {
|
ret = rk628_hdmirx_init(rk628);
|
if (ret < 0)
|
return;
|
}
|
|
hdmirx = rk628->hdmirx;
|
if (!tx_5v_power_present(rk628)) {
|
hdmirx->plugin = false;
|
rk628_hdmirx_disable_edid(rk628);
|
rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0, SW_I2S_DATA_OEN_MASK,
|
SW_I2S_DATA_OEN(1));
|
dev_info(rk628->dev, "hdmirx plug out\n");
|
}
|
}
|
|
int rk628_hdmirx_detect(struct rk628 *rk628)
|
{
|
int ret = 0;
|
struct rk628_hdmirx *hdmirx;
|
|
if (!rk628->hdmirx) {
|
ret = rk628_hdmirx_init(rk628);
|
if (ret < 0 || !rk628->hdmirx)
|
return HDMIRX_PLUGOUT;
|
}
|
hdmirx = rk628->hdmirx;
|
|
if (tx_5v_power_present(rk628)) {
|
ret |= HDMIRX_PLUGIN;
|
if (!hdmirx->plugin)
|
ret |= HDMIRX_CHANGED;
|
if (rk628_hdmirx_status_change(rk628))
|
ret |= HDMIRX_CHANGED;
|
if (!hdmirx->phy_lock)
|
ret |= HDMIRX_NOLOCK;
|
hdmirx->plugin = true;
|
} else {
|
ret |= HDMIRX_PLUGOUT;
|
if (hdmirx->plugin)
|
ret |= HDMIRX_CHANGED;
|
hdmirx->plugin = false;
|
}
|
|
return ret;
|
}
|
