// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/iopoll.h>
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#include "rkx110_x120.h"
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#include "rkx120_reg.h"
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#include "serdes_combphy.h"
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#define CLANE_PARA0 0x0000
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#define CLANE_PARA1 0x0004
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#define T_INITTIME_C(x) UPDATE(x, 31, 0)
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#define CLANE_PARA2 0x0008
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#define T_CLKPREPARE_C(x) UPDATE(x, 23, 16)
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#define T_CLKZERO_C(x) UPDATE(x, 15, 8)
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#define T_CLKPRE_C(x) UPDATE(x, 7, 0)
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#define CLANE_PARA3 0x000c
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#define T_CLKPOST_C_MASK GENMASK(23, 16)
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#define T_CLKPOST_C(x) UPDATE(x, 23, 16)
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#define T_CLKTRAIL_C_MASK GENMASK(15, 8)
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#define T_CLKTRAIL_C(x) UPDATE(x, 15, 8)
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#define T_HSEXIT_C_MASK GENMASK(7, 0)
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#define T_HSEXIT_C(x) UPDATE(x, 7, 0)
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#define DLANE0_PARA0 0x0010
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#define T_RST2ENLPTX_D(x) UPDATE(x, 15, 0)
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#define DLANE0_PARA1 0x0014
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#define T_INITTIME_D(x) UPDATE(x, 31, 0)
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#define DLANE0_PARA2 0x0018
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#define T_HSPREPARE_D(x) UPDATE(x, 31, 24)
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#define T_HSZERO_D(x) UPDATE(x, 23, 16)
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#define T_HSTRAIL_D(x) UPDATE(x, 15, 8)
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#define T_HSEXIT_D(x) UPDATE(x, 7, 0)
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#define DLANE0_PARA3 0x001c
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#define T_WAKEUP_D(x) UPDATE(x, 31, 0)
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#define DLANE0_PARA4 0x0020
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#define T_TAGO_D0(x) UPDATE(x, 23, 16)
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#define T_TASURE_D0(x) UPDATE(x, 15, 8)
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#define T_TAGET_D0(x) UPDATE(x, 7, 0)
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#define DLANE_PARA0(x) (0x0014 + (x * 0x0010))
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#define DLANE_PARA1(x) (0x0018 + (x * 0x0010))
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#define DLANE_PARA2(x) (0x001C + (x * 0x0010))
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#define DLANE_PARA3(x) (0x0020 + (x * 0x0010))
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#define COMMON_PARA0 (0x0054)
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#define T_LPX(x) UPDATE(x, 7, 0)
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#define CTRL_PARA0 0x0058
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#define PWON_SEL BIT(3)
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#define PWON_DSI BIT(1)
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#define SU_IDDQ_EN BIT(0)
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#define PLL_CTRL_PARA0 0x005c
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#define PLL_LOCK BIT(27)
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#define RATE_MASK GENMASK(26, 24)
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#define RATE(x) UPDATE(x, 26, 24)
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#define REFCLK_DIV_MASK GENMASK(23, 19)
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#define REFCLK_DIV(x) UPDATE(x, 23, 19)
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#define PLL_DIV_MASK GENMASK(18, 4)
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#define PLL_DIV(x) UPDATE(x, 18, 4)
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#define DSI_PIXELCLK_DIV(x) UPDATE(x, 3, 0)
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#define PLL_CTRL_PARA1 0x0060
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#define PLL_CTRL(x) UPDATE(x, 31, 0)
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#define RCAL_CTRL 0x0064
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#define RCAL_EN BIT(13)
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#define RCAL_TRIM(x) UPDATE(x, 12, 9)
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#define RCAL_DONE BIT(0)
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#define TRIM_PARA 0x0068
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#define HSTX_AMP_TRIM(x) UPDATE(x, 13, 11)
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#define LPTX_SR_TRIM(x) UPDATE(x, 10, 8)
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#define LPRX_VREF_TRIM(x) UPDATE(x, 7, 4)
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#define LPCD_VREF_TRIM(x) UPDATE(x, 3, 0)
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#define TEST_PARA0 0x006c
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#define FSET_EN BIT(3)
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#define CLANE_PARA4 0x0078
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#define INTERFACE_PARA 0x007c
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#define TXREADYESC_VLD(x) UPDATE(x, 15, 8)
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#define RXVALIDESC_VLD(x) UPDATE(x, 7, 0)
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#define GRF_MIPITX_CON0 0x0000
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#define PHYSHUTDWN(x) HIWORD_UPDATE(x, GENMASK(10, 10), 10)
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#define LVDS_REFCLK_DIV(x) HIWORD_UPDATE(x, GENMASK(9, 6), 6)
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#define PHY_MODE(x) HIWORD_UPDATE(x, GENMASK(4, 3), 3)
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#define RATE_LVDS(x) HIWORD_UPDATE(x, GENMASK(2, 1), 1)
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#define GRF_MIPITX_CON1 0x0004
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#define PWON_PLL(x) HIWORD_UPDATE(x, GENMASK(15, 15), 15)
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#define LVDS_PLL_DIV(x) HIWORD_UPDATE(x, GENMASK(14, 0), 0)
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#define GRF_MIPITX_CON5 0x0014
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#define TXCLK_BUS_WIDTH(x) HIWORD_UPDATE(x, GENMASK(14, 12), 12)
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#define TX3_BUS_WIDTH(x) HIWORD_UPDATE(x, GENMASK(11, 9), 9)
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#define TX2_BUS_WIDTH(x) HIWORD_UPDATE(x, GENMASK(8, 6), 6)
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#define TX1_BUS_WIDTH(x) HIWORD_UPDATE(x, GENMASK(5, 3), 3)
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#define TX0_BUS_WIDTH(x) HIWORD_UPDATE(x, GENMASK(2, 0), 0)
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#define GRF_MIPITX_CON6 0x0018
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#define TX0_CTL_LOW(x) HIWORD_UPDATE(x, GENMASK(15, 0), 0)
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#define GRF_MIPITX_CON7 0x001c
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#define TX1_CTL_LOW(x) HIWORD_UPDATE(x, GENMASK(15, 0), 0)
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#define GRF_MIPITX_CON8 0x0020
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#define TX2_CTL_LOW(x) HIWORD_UPDATE(x, GENMASK(15, 0), 0)
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#define GRF_MIPITX_CON9 0x0024
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#define TX3_CTL_LOW(x) HIWORD_UPDATE(x, GENMASK(15, 0), 0)
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#define GRF_MIPITX_CON10 0x0028
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#define TXCK_CTL_LOW(x) HIWORD_UPDATE(x, GENMASK(15, 0), 0)
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#define GRF_MIPITX_CON13 0x0034
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#define TX_IDLE(x) HIWORD_UPDATE(x, GENMASK(4, 0), 0)
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#define GRF_MIPITX_CON14 0x0038
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#define TX_PD(x) HIWORD_UPDATE(x, GENMASK(14, 10), 10)
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#define GRF_MIPI_STATUS 0x0080
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#define PHYLOCK BIT(0)
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static void rkx120_combtxphy_dsi_timing_init(struct rk_serdes *des, u8 remote_id)
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{
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struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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const struct configure_opts_combphy cfg = combtxphy->mipi_dphy_cfg;
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u32 byte_clk = DIV_ROUND_CLOSEST_ULL(combtxphy->rate, 8);
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u32 esc_div = DIV_ROUND_UP(byte_clk, 20 * USEC_PER_SEC);
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u64 t_byte_clk = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, byte_clk);
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u32 t_clkprepare, t_clkzero, t_clkpre, t_clkpost, t_clktrail;
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u32 t_init, t_hsexit, t_hsprepare, t_hszero, t_wakeup, t_hstrail;
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u32 t_tago, t_tasure, t_taget;
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u32 base = RKX120_MIPI_LVDS_TX_PHY0_BASE;
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serdes_combphy_write(des, remote_id, base + INTERFACE_PARA,
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TXREADYESC_VLD(esc_div - 2) |
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RXVALIDESC_VLD(esc_div - 2));
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serdes_combphy_write(des, remote_id, base + COMMON_PARA0, esc_div);
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serdes_combphy_update_bits(des, remote_id, base + TEST_PARA0, FSET_EN, FSET_EN);
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t_init = DIV_ROUND_UP(cfg.init, t_byte_clk) - 1;
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serdes_combphy_write(des, remote_id, base + CLANE_PARA1, T_INITTIME_C(t_init));
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serdes_combphy_write(des, remote_id, base + DLANE0_PARA1, T_INITTIME_D(t_init));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA1(1), T_INITTIME_D(t_init));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA1(2), T_INITTIME_D(t_init));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA1(3), T_INITTIME_D(t_init));
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t_clkprepare = DIV_ROUND_UP(cfg.clk_prepare, t_byte_clk) - 1;
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t_clkzero = DIV_ROUND_UP(cfg.clk_zero, t_byte_clk) - 1;
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t_clkpre = DIV_ROUND_UP(cfg.clk_pre, t_byte_clk) - 1;
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serdes_combphy_write(des, remote_id, base + CLANE_PARA2,
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T_CLKPREPARE_C(t_clkprepare) |
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T_CLKZERO_C(t_clkzero) | T_CLKPRE_C(t_clkpre));
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t_clkpost = DIV_ROUND_UP(cfg.clk_post, t_byte_clk) - 1;
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t_clktrail = DIV_ROUND_UP(cfg.clk_trail, t_byte_clk) - 1;
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t_hsexit = DIV_ROUND_UP(cfg.hs_exit, t_byte_clk) - 1;
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serdes_combphy_write(des, remote_id, base + CLANE_PARA3,
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T_CLKPOST_C(t_clkpost) |
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T_CLKTRAIL_C(t_clktrail) |
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T_HSEXIT_C(t_hsexit));
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t_hsprepare = DIV_ROUND_UP(cfg.hs_prepare, t_byte_clk) - 1;
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t_hszero = DIV_ROUND_UP(cfg.hs_zero, t_byte_clk) - 1;
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t_hstrail = DIV_ROUND_UP(cfg.hs_trail, t_byte_clk) - 1;
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serdes_combphy_write(des, remote_id, base + DLANE0_PARA2,
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T_HSPREPARE_D(t_hsprepare) |
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T_HSZERO_D(t_hszero) |
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T_HSTRAIL_D(t_hstrail) |
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T_HSEXIT_D(t_hsexit));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA2(1),
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T_HSPREPARE_D(t_hsprepare) |
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T_HSZERO_D(t_hszero) |
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T_HSTRAIL_D(t_hstrail) |
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T_HSEXIT_D(t_hsexit));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA2(2),
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T_HSPREPARE_D(t_hsprepare) |
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T_HSZERO_D(t_hszero) |
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T_HSTRAIL_D(t_hstrail) |
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T_HSEXIT_D(t_hsexit));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA2(3),
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T_HSPREPARE_D(t_hsprepare) |
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T_HSZERO_D(t_hszero) |
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T_HSTRAIL_D(t_hstrail) |
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T_HSEXIT_D(t_hsexit));
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t_wakeup = DIV_ROUND_UP(cfg.wakeup, t_byte_clk) - 1;
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serdes_combphy_write(des, remote_id, base + DLANE0_PARA3, T_WAKEUP_D(t_wakeup));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA3(1), T_WAKEUP_D(t_wakeup));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA3(2), T_WAKEUP_D(t_wakeup));
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serdes_combphy_write(des, remote_id, base + DLANE_PARA3(3), T_WAKEUP_D(t_wakeup));
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serdes_combphy_write(des, remote_id, base + CLANE_PARA4, T_WAKEUP_D(t_wakeup));
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t_tago = DIV_ROUND_UP(cfg.ta_go, t_byte_clk) - 1;
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t_tasure = DIV_ROUND_UP(cfg.ta_sure, t_byte_clk) - 1;
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t_taget = DIV_ROUND_UP(cfg.ta_get, t_byte_clk) - 1;
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serdes_combphy_write(des, remote_id, base + DLANE0_PARA4,
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T_TAGO_D0(t_tago) |
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T_TASURE_D0(t_tasure) |
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T_TAGET_D0(t_taget));
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}
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static void rkx120_combtxphy_dsi_pll_set(struct rk_serdes *des, u8 remote_id)
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{
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struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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u32 base = RKX120_MIPI_LVDS_TX_PHY0_BASE;
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serdes_combphy_update_bits(des, remote_id, base + PLL_CTRL_PARA0,
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RATE_MASK | REFCLK_DIV_MASK | PLL_DIV_MASK,
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RATE(combtxphy->rate_factor) |
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REFCLK_DIV(combtxphy->ref_div - 1) |
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PLL_DIV(combtxphy->fb_div));
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}
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static void rkx120_combtxphy_dsi_power_on(struct rk_serdes *des, u8 remote_id)
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{
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struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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struct i2c_client *client = des->chip[remote_id].client;
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u32 grf_base = RKX120_GRF_MIPI0_BASE;
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u32 val;
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int ret;
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON0,
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PHY_MODE(COMBTX_PHY_MODE_VIDEO_MIPI));
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serdes_combphy_get_default_config(combtxphy->rate, &combtxphy->mipi_dphy_cfg);
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rkx120_combtxphy_dsi_timing_init(des, remote_id);
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rkx120_combtxphy_dsi_pll_set(des, remote_id);
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON0, PHYSHUTDWN(1));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON1, PWON_PLL(1));
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ret = read_poll_timeout(des->i2c_read_reg, ret,
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!(ret < 0) && (val & PLL_LOCK),
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0, MSEC_PER_SEC, false, client,
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RKX120_MIPI_LVDS_TX_PHY0_BASE + PLL_CTRL_PARA0,
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&val);
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if (ret < 0)
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dev_err(des->dev, "PLL is not locked\n");
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}
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static void rkx120_combtxphy_dsi_power_off(struct rk_serdes *des, u8 remote_id)
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{
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struct i2c_client *client = des->chip[remote_id].client;
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u32 grf_base = RKX120_GRF_MIPI0_BASE;
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON0, PHYSHUTDWN(0));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON1, PWON_PLL(0));
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}
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static void rkx120_combtxphy_lvds_power_on(struct rk_serdes *des, u8 remote_id, u8 phy_id)
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{
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struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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struct i2c_client *client = des->chip[remote_id].client;
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u32 grf_base = (phy_id == 0) ?
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RKX120_GRF_MIPI0_BASE : RKX120_GRF_MIPI1_BASE;
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const struct {
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unsigned long max_lane_mbps;
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u8 rate_lvds;
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u8 refclk_div;
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u16 pll_div;
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} hsfreqrange_table[] = {
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{250, 2, 0, 0x3800},
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{500, 1, 1, 0x3800},
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{1000, 0, 3, 0x3800},
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};
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int ret;
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u32 val;
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u8 index;
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for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
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if (combtxphy->rate < hsfreqrange_table[index].max_lane_mbps * USEC_PER_SEC)
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break;
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if (index == ARRAY_SIZE(hsfreqrange_table))
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--index;
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON13, TX_IDLE(0x1f));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON14, TX_PD(0x1f));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON0,
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LVDS_REFCLK_DIV(hsfreqrange_table[index].refclk_div) |
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RATE_LVDS(hsfreqrange_table[index].rate_lvds));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON1,
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LVDS_PLL_DIV(hsfreqrange_table[index].pll_div));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON5,
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TXCLK_BUS_WIDTH(2) | TX3_BUS_WIDTH(2) |
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TX2_BUS_WIDTH(2) | TX1_BUS_WIDTH(2) |
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TX0_BUS_WIDTH(2));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON6, TX0_CTL_LOW(0x80));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON7, TX0_CTL_LOW(0x80));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON8, TX0_CTL_LOW(0x80));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON9, TX0_CTL_LOW(0x80));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON10, TX0_CTL_LOW(0x80));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON14, TX_PD(0));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON0, PHYSHUTDWN(1) |
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PHY_MODE(COMBTX_PHY_MODE_VIDEO_LVDS));
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON1, PWON_PLL(1));
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ret = read_poll_timeout(des->i2c_read_reg, ret,
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!(ret < 0) && (val & PHYLOCK),
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0, MSEC_PER_SEC, false, client,
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grf_base + GRF_MIPI_STATUS, &val);
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if (ret < 0)
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dev_err(des->dev, "PLL is not locked\n");
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des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON13, TX_IDLE(0));
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}
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void rkx120_combtxphy_power_on(struct rk_serdes *des, u8 remote_id, u8 phy_id)
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{
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struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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switch (combtxphy->mode) {
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case COMBTX_PHY_MODE_VIDEO_MIPI:
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rkx120_combtxphy_dsi_power_on(des, remote_id);
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break;
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case COMBTX_PHY_MODE_VIDEO_LVDS:
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rkx120_combtxphy_lvds_power_on(des, remote_id, phy_id);
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break;
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default:
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break;
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}
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}
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void rkx120_combtxphy_power_off(struct rk_serdes *des, u8 remote_id)
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{
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struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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switch (combtxphy->mode) {
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case COMBTX_PHY_MODE_VIDEO_MIPI:
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rkx120_combtxphy_dsi_power_off(des, remote_id);
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break;
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case COMBTX_PHY_MODE_VIDEO_LVDS:
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break;
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case COMBTX_PHY_MODE_GPIO:
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break;
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default:
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break;
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}
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}
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static void rkx120_combtxphy_dsi_pll_calc_rate(struct rkx120_combtxphy *combtxphy, u64 rate)
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{
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const struct {
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unsigned long max_lane_mbps;
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u8 refclk_div;
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u8 post_factor;
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} hsfreqrange_table[] = {
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{ 100, 1, 5 },
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{ 200, 1, 4 },
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{ 400, 1, 3 },
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{ 800, 1, 2},
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{ 1600, 1, 1},
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};
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u64 ref_clk = 24 * USEC_PER_SEC;
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u64 fvco;
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u16 fb_div;
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u8 ref_div, post_div, index;
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for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
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if (rate <= hsfreqrange_table[index].max_lane_mbps * USEC_PER_SEC)
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break;
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if (index == ARRAY_SIZE(hsfreqrange_table))
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--index;
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/*
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* FVCO = Fckref * 8 * （ PI_POST_DIV + PF_POST_DIV） / R
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* data_rate = FVCO / post_div;
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*/
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ref_div = hsfreqrange_table[index].refclk_div;
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post_div = 1 << hsfreqrange_table[index].post_factor;
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fvco = rate * post_div;
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fb_div = DIV_ROUND_CLOSEST_ULL((fvco * ref_div) << 10, ref_clk * 8);
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rate = DIV_ROUND_CLOSEST_ULL(ref_clk * 8 * fb_div,
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(u64)(ref_div * post_div) << 10);
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combtxphy->ref_div = ref_div;
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combtxphy->fb_div = fb_div;
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combtxphy->rate_factor = hsfreqrange_table[index].post_factor;
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combtxphy->rate = rate;
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}
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static void rkx120_combtxphy_lvds_pll_calc_rate(struct rkx120_combtxphy *combtxphy, u64 rate)
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{
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}
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void rkx120_combtxphy_set_rate(struct rk_serdes *des, u64 rate)
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{
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struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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switch (combtxphy->mode) {
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case COMBTX_PHY_MODE_VIDEO_MIPI:
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rkx120_combtxphy_dsi_pll_calc_rate(combtxphy, rate);
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break;
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case COMBTX_PHY_MODE_VIDEO_LVDS:
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rkx120_combtxphy_lvds_pll_calc_rate(combtxphy, rate);
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break;
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default:
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break;
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}
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combtxphy->rate = rate;
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}
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u64 rkx120_combtxphy_get_rate(struct rk_serdes *des)
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{
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return des->combtxphy.rate;
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}
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void rkx120_combtxphy_set_mode(struct rk_serdes *des, enum combtx_phy_mode mode)
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{
|
struct rkx120_combtxphy *combtxphy = &des->combtxphy;
|
|
combtxphy->mode = mode;
|
}
|
