/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Rockchip Electronics Co. Ltd.
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*
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* Author: Joseph Chen <chenjh@rock-chips.com>
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*/
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#ifndef _CRU_RKX120_H
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#include "cru_core.h"
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// ======================== TXCRU module definition START ======================
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// TXCRU_SOFTRST_CON01(Offset:0x404)
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#define RKX120_SRST_PRESETN_TX_CRU 0x00000010
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#define RKX120_SRST_PRESETN_TX_GRF 0x00000011
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#define RKX120_SRST_PRESETN_TX_GPIO0 0x00000012
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#define RKX120_SRST_DRESETN_TX_GPIO0 0x00000013
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#define RKX120_SRST_PRESETN_TX_GPIO1 0x00000014
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#define RKX120_SRST_DRESETN_TX_GPIO1 0x00000015
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#define RKX120_SRST_PRESETN_TX_EFUSE 0x00000016
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#define RKX120_SRST_RESETN_TX_EFUSE 0x00000017
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#define RKX120_SRST_PRESETN_MIPI_GRF_TX0 0x0000001A
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#define RKX120_SRST_PRESETN_MIPI_GRF_TX1 0x0000001B
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#define RKX120_SRST_PRESETN_TX_I2C2APB 0x0000001E
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#define RKX120_SRST_PRESETN_TX_I2C2APB_DEBUG 0x0000001F
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// TXCRU_SOFTRST_CON02(Offset:0x408)
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#define RKX120_SRST_HRESETN_DVP_TX 0x00000020
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// TXCRU_SOFTRST_CON03(Offset:0x40C)
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#define RKX120_SRST_PRESETN_CSITX0 0x00000030
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#define RKX120_SRST_RESETN_TXBYTEHS_CSITX0 0x00000031
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#define RKX120_SRST_RESETN_TXESC_CSITX0 0x00000032
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#define RKX120_SRST_PRESETN_CSITX1 0x00000034
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#define RKX120_SRST_RESETN_TXBYTEHS_CSITX1 0x00000035
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#define RKX120_SRST_RESETN_TXESC_CSITX1 0x00000036
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#define RKX120_SRST_PRESETN_DSITX 0x00000038
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// TXCRU_SOFTRST_CON04(Offset:0x410)
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#define RKX120_SRST_PRESETN_RKLINK_RX 0x00000040
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#define RKX120_SRST_RESETN_I2S_SRC_RKLINK_RX 0x00000041
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#define RKX120_SRST_RESETN_E0_RKLINK_RX 0x00000045
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#define RKX120_SRST_IRESETN_C_CSI0 0x00000046
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#define RKX120_SRST_RESETN_E1_RKLINK_RX 0x00000049
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#define RKX120_SRST_IRESETN_C_CSI1 0x0000004A
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// TXCRU_SOFTRST_CON05(Offset:0x414)
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#define RKX120_SRST_DRESETN_C_DVP 0x00000051
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#define RKX120_SRST_RESETN_LVDS0 0x0000005B
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#define RKX120_SRST_RESETN_LVDS1 0x0000005D
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// TXCRU_SOFTRST_CON06(Offset:0x418)
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#define RKX120_SRST_RESETN_PMA2PCS2LINK_LINK 0x00000061
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#define RKX120_SRST_RESETN_PMA2PCS2LINK_PCS0 0x00000062
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#define RKX120_SRST_RESETN_PMA2PCS2LINK_PCS1 0x00000063
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#define RKX120_SRST_PRESETN_D_DSI_PATTERN_GEN 0x00000064
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#define RKX120_SRST_PRESETN_LVDS0_PATTERN_GEN 0x00000065
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#define RKX120_SRST_PRESETN_LVDS1_PATTERN_GEN 0x00000066
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#define RKX120_SRST_DRESETN_D_DSI_PATTERN_GEN 0x00000067
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#define RKX120_SRST_RESETN_LVDS0_PATTERN_GEN 0x00000068
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#define RKX120_SRST_RESETN_LVDS1_PATTERN_GEN 0x00000069
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// TXCRU_SOFTRST_CON07(Offset:0x41C)
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#define RKX120_SRST_PRESETN_PCS0 0x00000070
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#define RKX120_SRST_RESETN_2X_PMA2PCS0 0x00000071
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#define RKX120_SRST_RESETN_LINK_PCS0 0x00000073
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#define RKX120_SRST_PRESETN_PCS0_ADA 0x00000074
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#define RKX120_SRST_RESETN_PCS0_ADA 0x00000075
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// TXCRU_SOFTRST_CON08(Offset:0x420)
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#define RKX120_SRST_PRESETN_PCS1 0x00000080
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#define RKX120_SRST_RESETN_2X_PMA2PCS1 0x00000081
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#define RKX120_SRST_RESETN_LINK_PCS1 0x00000083
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#define RKX120_SRST_PRESETN_PCS1_ADA 0x00000084
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#define RKX120_SRST_RESETN_PCS1_ADA 0x00000085
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// TXCRU_SOFTRST_CON09(Offset:0x424)
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#define RKX120_SRST_PRESETN_DVPTX 0x00000090
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#define RKX120_SRST_PRESETN_MIPITXPHY0 0x00000098
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#define RKX120_SRST_RESETN_MIPITXPHY0 0x00000099
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#define RKX120_SRST_PRESETN_MIPITXPHY1 0x0000009A
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#define RKX120_SRST_RESETN_MIPITXPHY1 0x0000009B
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// TXCRU_SOFTRST_CON10(Offset:0x428)
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#define RKX120_SRST_PRESETN_PWM_TX 0x000000A0
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#define RKX120_SRST_RESETN_PWM_TX 0x000000A1
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// TXCRU_SOFTRST_CON11(Offset:0x42C)
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#define RKX120_SRST_PRESETN_DFT2APB 0x000000B0
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// TXCRU_GATE_CON00(Offset:0x300)
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#define RKX120_CLK_TESTOUT_TOP_GATE 0x00000000
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#define RKX120_BUSCLK_TX_PRE0_GATE 0x00000001
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#define RKX120_BUSCLK_TX_PRE_GATE 0x00000002
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// TXCRU_GATE_CON01(Offset:0x304)
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#define RKX120_PCLK_TX_CRU_GATE 0x00000010
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#define RKX120_PCLK_TX_GRF_GATE 0x00000011
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#define RKX120_PCLK_TX_GPIO0_GATE 0x00000012
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#define RKX120_DCLK_TX_GPIO0_GATE 0x00000013
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#define RKX120_PCLK_TX_GPIO1_GATE 0x00000014
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#define RKX120_DCLK_TX_GPIO1_GATE 0x00000015
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#define RKX120_PCLK_TX_EFUSE_GATE 0x00000016
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#define RKX120_CLK_TX_EFUSE_GATE 0x00000017
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#define RKX120_PCLK_MIPI_GRF_TX0_GATE 0x0000001A
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#define RKX120_PCLK_MIPI_GRF_TX1_GATE 0x0000001B
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#define RKX120_PCLK_TX_I2C2APB_GATE 0x0000001E
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#define RKX120_PCLK_TX_I2C2APB_DEBUG_GATE 0x0000001F
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// TXCRU_GATE_CON02(Offset:0x308)
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#define RKX120_HCLK_DVP_TX_GATE 0x00000020
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// TXCRU_GATE_CON03(Offset:0x30C)
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#define RKX120_PCLK_CSITX0_GATE 0x00000030
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#define RKX120_CLK_TXBYTEHS_DSITX_CSITX0_DFT_GATE 0x00000031
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#define RKX120_CLK_TXESC_CSITX0_GATE 0x00000032
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#define RKX120_PCLK_CSITX1_GATE 0x00000034
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#define RKX120_CLK_TXBYTEHS_CSITX1_DFT_GATE 0x00000035
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#define RKX120_CLK_TXESC_CSITX1_GATE 0x00000036
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#define RKX120_PCLK_DSITX_GATE 0x00000038
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#define RKX120_CLK_RXESC_DSITX_DFT_GATE 0x0000003A
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// TXCRU_GATE_CON04(Offset:0x310)
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#define RKX120_PCLK_RKLINK_RX_GATE 0x00000040
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#define RKX120_CLK_I2S_SRC_RKLINK_RX_GATE 0x00000041
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#define RKX120_E0_CLK_RKLINK_RX_PRE_GATE 0x00000044
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#define RKX120_E0_CLK_RKLINK_RX_GATE 0x00000045
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#define RKX120_ICLK_C_CSI0_GATE 0x00000046
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#define RKX120_E1_CLK_RKLINK_RX_PRE_GATE 0x00000048
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#define RKX120_E1_CLK_RKLINK_RX_GATE 0x00000049
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#define RKX120_ICLK_C_CSI1_GATE 0x0000004A
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// TXCRU_GATE_CON05(Offset:0x314)
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#define RKX120_DCLK_RGB_GATE 0x00000050
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#define RKX120_DCLK_C_DVP_GATE 0x00000051
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#define RKX120_DCLK_D_DSI_CM_GATE 0x00000058
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#define RKX120_DCLK_D_DSI_GATE 0x00000059
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#define RKX120_CLK_LVDS0_CM_GATE 0x0000005A
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#define RKX120_CLK_LVDS0_GATE 0x0000005B
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#define RKX120_CLK_LVDS1_CM_GATE 0x0000005C
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#define RKX120_CLK_LVDS1_GATE 0x0000005D
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// TXCRU_GATE_CON06(Offset:0x318)
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#define RKX120_CLK_PMA2PCS2LINK_CM_GATE 0x00000060
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#define RKX120_CLK_PMA2PCS2LINK_LINK_GATE 0x00000061
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#define RKX120_CLK_PMA2PCS2LINK_PCS0_GATE 0x00000062
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#define RKX120_CLK_PMA2PCS2LINK_PCS1_GATE 0x00000063
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#define RKX120_PCLK_D_DSI_PATTERN_GEN_GATE 0x00000064
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#define RKX120_PCLK_LVDS0_PATTERN_GEN_GATE 0x00000065
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#define RKX120_PCLK_LVDS1_PATTERN_GEN_GATE 0x00000066
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#define RKX120_DCLK_D_DSI_PATTERN_GEN_GATE 0x00000067
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#define RKX120_CLK_LVDS0_PATTERN_GEN_GATE 0x00000068
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#define RKX120_CLK_LVDS1_PATTERN_GEN_GATE 0x00000069
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// TXCRU_GATE_CON07(Offset:0x31C)
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#define RKX120_PCLK_PCS0_GATE 0x00000070
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#define RKX120_CLK_2X_PMA2PCS0_DFT_GATE 0x00000071
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#define RKX120_CLK_LINK_PCS0_DFT_GATE 0x00000072
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#define RKX120_CLK_LINK_PCS0_GATE 0x00000073
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#define RKX120_PCLK_PCS0_ADA_GATE 0x00000074
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#define RKX120_CLK_PCS0_ADA_GATE 0x00000075
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// TXCRU_GATE_CON08(Offset:0x320)
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#define RKX120_PCLK_PCS1_GATE 0x00000080
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#define RKX120_CLK_2X_PMA2PCS1_DFT_GATE 0x00000081
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#define RKX120_CLK_LINK_PCS1_DFT_GATE 0x00000082
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#define RKX120_CLK_LINK_PCS1_GATE 0x00000083
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#define RKX120_PCLK_PCS1_ADA_GATE 0x00000084
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#define RKX120_CLK_PCS1_ADA_GATE 0x00000085
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// TXCRU_GATE_CON09(Offset:0x324)
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#define RKX120_PCLKOUT_DVPTX_GATE 0x00000090
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#define RKX120_PCLK_MIPITXPHY0_GATE 0x00000098
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#define RKX120_PCLK_MIPITXPHY1_GATE 0x0000009A
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// TXCRU_GATE_CON10(Offset:0x328)
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#define RKX120_PCLK_PWM_TX_GATE 0x000000A0
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#define RKX120_CLK_PWM_TX_GATE 0x000000A1
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#define RKX120_CLK_CAPTURE_PWM_TX_GATE 0x000000A2
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#define RKX120_CLK_TXESC_MIPITXPHY0_GATE 0x000000A8
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// TXCRU_GATE_CON11(Offset:0x32C)
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#define RKX120_PCLK_DFT2APB_GATE 0x000000B0
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// TXCRU_CLKSEL_CON00(Offset:0x100)
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#define RKX120_TEST_CLKOUT_IOUT_DIV 0x08000000
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#define RKX120_TEST_CLKOUT_IOUT_SEL 0x05080000
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#define RKX120_TEST_CLKOUT_IOUT_SEL_XIN_OSC0_FUNC 0U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXPLL_MUX 1U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_CPLL_MUX 2U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXBYTEHS_CSITX0 3U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXESC_CSITX0 4U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXBYTEHS_CSITX1 5U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXESC_CSITX1 6U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXBYTEHS_DSITX 7U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_RXESC_DSITX 8U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_LINK_PCS0 9U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_LINK_PCS1 10U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_PMARX0_PIXEL 11U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_PMARX1_PIXEL 12U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_MIPITXPHY0_LVDS 13U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_MIPITXPHY0_PIXEL 14U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_MIPITXPHY1_LVDS 15U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_TESTCLK_MIPITXPHY1_PIXEL 16U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_BUSCLK_TX_PRE 17U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_I2S_SRC_RKLINK_RX 20U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_E0_CLK_RKLINK_RX_PRE 21U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_PCLKOUT_DVPTX 22U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXBYTEHS_DSITX_CSITX0 23U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_DCLK_C_DVP_SRC 24U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_DCLK_D_DSI_SRC 25U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_LVDS0_SRC 26U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_LVDS1_SRC 27U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_DCLK_RGB_SRC 28U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_2X_PMA2PCS0 29U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_2X_PMA2PCS1 30U
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#define RKX120_TEST_CLKOUT_IOUT_SEL_CLK_TXESC_MIPITXPHY0 31U
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// TXCRU_CLKSEL_CON01(Offset:0x104)
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#define RKX120_BUSCLK_TX_PRE0_DIV 0x06000001
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#define RKX120_BUSCLK_TX_PRE0_SEL 0x01070001
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#define RKX120_BUSCLK_TX_PRE0_SEL_CLK_TXPLL_MUX 0U
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#define RKX120_BUSCLK_TX_PRE0_SEL_CLK_CPLL_MUX 1U
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#define RKX120_BUSCLK_TX_PRE_SEL 0x01080001
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#define RKX120_BUSCLK_TX_PRE_SEL_XIN_OSC0_FUNC 0U
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#define RKX120_BUSCLK_TX_PRE_SEL_BUSCLK_TX_PRE0 1U
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// TXCRU_CLKSEL_CON03(Offset:0x10C)
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#define RKX120_CLK_TXESC_CSITX0_DIV 0x08000003
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#define RKX120_CLK_TXESC_CSITX0_SEL 0x020E0003
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#define RKX120_CLK_TXESC_CSITX0_SEL_CLK_TXPLL_MUX 0U
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#define RKX120_CLK_TXESC_CSITX0_SEL_CLK_CPLL_MUX 1U
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#define RKX120_CLK_TXESC_CSITX0_SEL_XIN_OSC0_FUNC 2U
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// TXCRU_CLKSEL_CON04(Offset:0x110)
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#define RKX120_CLK_TXESC_CSITX1_DIV 0x08000004
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#define RKX120_CLK_TXESC_CSITX1_SEL 0x020E0004
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#define RKX120_CLK_TXESC_CSITX1_SEL_CLK_TXPLL_MUX 0U
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#define RKX120_CLK_TXESC_CSITX1_SEL_CLK_CPLL_MUX 1U
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#define RKX120_CLK_TXESC_CSITX1_SEL_XIN_OSC0_FUNC 2U
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// TXCRU_CLKSEL_CON05(Offset:0x114)
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#define RKX120_CLK_I2S_SRC_RKLINK_RX_DIV 0x08000005
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#define RKX120_CLK_I2S_SRC_RKLINK_RX_SEL 0x020E0005
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#define RKX120_CLK_I2S_SRC_RKLINK_RX_SEL_CLK_TXPLL_MUX 0U
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#define RKX120_CLK_I2S_SRC_RKLINK_RX_SEL_CLK_CPLL_MUX 1U
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#define RKX120_CLK_I2S_SRC_RKLINK_RX_SEL_XIN_OSC0_FUNC 2U
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// TXCRU_CLKSEL_CON06(Offset:0x118)
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#define RKX120_E0_CLK_RKLINK_RX_PRE_DIV 0x08000006
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#define RKX120_E0_CLK_RKLINK_RX_PRE_SEL 0x020E0006
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#define RKX120_E0_CLK_RKLINK_RX_PRE_SEL_CLK_TXPLL_MUX 0U
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#define RKX120_E0_CLK_RKLINK_RX_PRE_SEL_CLK_CPLL_MUX 1U
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#define RKX120_E0_CLK_RKLINK_RX_PRE_SEL_XIN_OSC0_FUNC 2U
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// TXCRU_CLKSEL_CON07(Offset:0x11C)
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#define RKX120_E1_CLK_RKLINK_RX_PRE_DIV 0x08000007
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#define RKX120_E1_CLK_RKLINK_RX_PRE_SEL 0x020E0007
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#define RKX120_E1_CLK_RKLINK_RX_PRE_SEL_CLK_TXPLL_MUX 0U
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#define RKX120_E1_CLK_RKLINK_RX_PRE_SEL_CLK_CPLL_MUX 1U
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#define RKX120_E1_CLK_RKLINK_RX_PRE_SEL_XIN_OSC0_FUNC 2U
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// TXCRU_CLKSEL_CON08(Offset:0x120)
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#define RKX120_CLK_PMA2PCS2LINK_CM_SEL 0x01000008
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#define RKX120_CLK_PMA2PCS2LINK_CM_SEL_CLK_LINK_PCS0_DFT 0U
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#define RKX120_CLK_PMA2PCS2LINK_CM_SEL_CLK_LINK_PCS1_DFT 1U
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// TXCRU_CLKSEL_CON10(Offset:0x128)
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#define RKX120_CLK_PWM_TX_DIV 0x0800000A
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#define RKX120_CLK_PWM_TX_SEL 0x020E000A
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#define RKX120_CLK_PWM_TX_SEL_CLK_TXPLL_MUX 0U
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#define RKX120_CLK_PWM_TX_SEL_CLK_CPLL_MUX 1U
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#define RKX120_CLK_PWM_TX_SEL_XIN_OSC0_FUNC 2U
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// TXCRU_CLKSEL_CON12(Offset:0x130)
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#define RKX120_PCLKOUT_DVPTX_DIV 0x0800000C
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#define RKX120_PCLKOUT_DVPTX_SEL 0x020E000C
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#define RKX120_PCLKOUT_DVPTX_SEL_CLK_TXPLL_MUX 0U
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#define RKX120_PCLKOUT_DVPTX_SEL_CLK_CPLL_MUX 1U
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#define RKX120_PCLKOUT_DVPTX_SEL_XIN_OSC0_FUNC 2U
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// ======================== TXCRU module definition END ========================
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#define RKX120_CPS_INVAL 0
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#define RKX120_CPS_PLL_CPLL 1
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#define RKX120_CPS_PLL_TXPLL 2
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#define RKX120_CPS_DCLK_TX_GPIO0 3
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#define RKX120_CPS_DCLK_TX_GPIO1 4
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#define RKX120_CPS_CLK_TX_EFUSE 5
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#define RKX120_CPS_CLK_PCS0_ADA 6
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#define RKX120_CPS_CLK_PCS1_ADA 7
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#define RKX120_CPS_CLK_CAPTURE_PWM_TX 8
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#define RKX120_CPS_ICLK_C_CSI0 9
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#define RKX120_CPS_ICLK_C_CSI1 10
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#define RKX120_CPS_CLK_TXESC_CSITX0 COMPOSITE_CLK(RKX120_CLK_TXESC_CSITX0_SEL, RKX120_CLK_TXESC_CSITX0_DIV)
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#define RKX120_CPS_CLK_TXESC_CSITX1 COMPOSITE_CLK(RKX120_CLK_TXESC_CSITX1_SEL, RKX120_CLK_TXESC_CSITX1_DIV)
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#define RKX120_CPS_CLK_I2S_SRC_RKLINK_RX COMPOSITE_CLK(RKX120_CLK_I2S_SRC_RKLINK_RX_SEL, RKX120_CLK_I2S_SRC_RKLINK_RX_DIV)
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#define RKX120_CPS_E0_CLK_RKLINK_RX_PRE COMPOSITE_CLK(RKX120_E0_CLK_RKLINK_RX_PRE_SEL, RKX120_E0_CLK_RKLINK_RX_PRE_DIV)
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#define RKX120_CPS_E1_CLK_RKLINK_RX_PRE COMPOSITE_CLK(RKX120_E1_CLK_RKLINK_RX_PRE_SEL, RKX120_E1_CLK_RKLINK_RX_PRE_DIV)
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#define RKX120_CPS_CLK_PMA2PCS2LINK_CM COMPOSITE_CLK(RKX120_CLK_PMA2PCS2LINK_CM_SEL, 0)
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#define RKX120_CPS_PCLKOUT_DVPTX COMPOSITE_CLK(RKX120_PCLKOUT_DVPTX_SEL, RKX120_PCLKOUT_DVPTX_DIV)
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#define RKX120_CPS_CLK_PWM_TX COMPOSITE_CLK(RKX120_CLK_PWM_TX_SEL, RKX120_CLK_PWM_TX_DIV)
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#define RKX120_CPS_BUSCLK_TX_PRE0 COMPOSITE_CLK(RKX120_BUSCLK_TX_PRE0_SEL, RKX120_BUSCLK_TX_PRE0_DIV)
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#define RKX120_CPS_BUSCLK_TX_PRE COMPOSITE_CLK(RKX120_BUSCLK_TX_PRE_SEL, 0)
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#define RKX120_CPS_TEST_CLKOUT COMPOSITE_CLK(RKX120_TEST_CLKOUT_IOUT_SEL, RKX120_TEST_CLKOUT_IOUT_DIV)
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#endif
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