// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Rockchip Electronics Co. Ltd.
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*
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* Author: Joseph Chen <chenjh@rock-chips.com>
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*/
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#include "cru_core.h"
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#include "cru_rkx120.h"
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/*
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* [RKX120 CHIP]: TX
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*
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* ================= SECITON: Input clock from devices =========================
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*
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* ### 300M ###
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* dclk_c_dvp_src
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* dclk_d_dsi_src --|-- dclk_d_ds
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* |-- dclk_d_dsi_pattern_gen
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*
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* clk_lvds0_src --|-- clk_lvds0
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* |-- clk_lvds0_pattern_gen
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*
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* clk_lvds1_src --|-- clk_lvds1
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* |-- clk_lvds1_pattern_gen
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*
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* dclk_rgc_src
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*
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*
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* ### 200M ###
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* clk_link_pcs0 --|-- clk_pma2pcs0 |-- clk_pma2link2pcs_link
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* | |
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* |-- clk_pma2link2pcs_cm (MUX) --|-- clk_pma2link2pcs_psc0
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* clk_link_pcs1 --| |
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* |-- clk_pma2pcs1 |-- clk_pma2link2pcs_psc1
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*
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* clk_txbytehs_dsitx_csitx0
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* clk_txbytehs_dsitx_csitx1
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*
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*
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*
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* ### 150M ###
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*
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* rxpclk_vicap_lvds
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*
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*
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* ### 100M ###
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*
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* clk_2x_pma2pcs0
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* clk_2x_pma2pcs1
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*
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*
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* ### 50M ###
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* clk_txesc_mipitxphy0
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* clk_rxesc_dsitx
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*
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*/
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#define RKX120_SSCG_TXPLL_EN 0
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#define RKX120_SSCG_CPLL_EN 0
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#define RKX120_TESTOUT_MUX -1 /* valid options: RKX120_TEST_CLKOUT_IOUT_SEL_? */
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#define RKX120_GRF_GPIO0B_IOMUX_H 0x0101000c
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#define GPIO0B7_TEST_CLKOUT 0x01c00080
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#define I2S_122888_BEST_PRATE 393216000
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#define I2S_112896_BEST_PRATE 756403200
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static struct PLL_CONFIG PLL_TABLE[] = {
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/* _mhz, _refDiv, _fbDiv, _postdDv1, _postDiv2, _dsmpd, _frac */
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RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
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RK_PLL_RATE(600000000, 1, 25, 1, 1, 1, 0),
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/* display */
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RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
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/* audio: 12.288M */
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RK_PLL_RATE(688128000, 1, 86, 3, 1, 0, 268435), /* div=56, vco=2064.384M */
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RK_PLL_RATE(393216000, 2, 131, 4, 1, 0, 1207959), /* div=32, vco=1572.864M */
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RK_PLL_RATE(344064000, 1, 43, 3, 1, 0, 134217), /* div=28, vco=1032.192M */
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/* audio: 11.2896M */
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RK_PLL_RATE(474163200, 1, 79, 4, 1, 0, 456340), /* div=42, vco=1896.6528M */
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RK_PLL_RATE(756403200, 1, 63, 2, 1, 0, 563714), /* div=67, vco=1512.8064M */
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RK_PLL_RATE(564480000, 1, 47, 2, 1, 0, 671088), /* div=50, vco=1128.96M */
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{ /* sentinel */ },
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};
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static struct PLL_SETUP TXPLL_SETUP = {
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.id = PLL_TXPLL,
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.conOffset0 = 0x01000020,
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.conOffset1 = 0x01000024,
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.conOffset2 = 0x01000028,
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.conOffset3 = 0x0100002c,
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.modeOffset = 0x01000600,
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.modeShift = 0, /* 0: slow-mode, 1: normal-mode */
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.lockShift = 10,
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.modeMask = 0x1,
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.rateTable = PLL_TABLE,
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.minRefdiv = 1,
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.maxRefdiv = 2,
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.minVco = _MHZ(375),
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.maxVco = _MHZ(2400),
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.minFout = _MHZ(24),
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.maxFout = _MHZ(1200),
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.sscgEn = RKX120_SSCG_TXPLL_EN,
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};
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static struct PLL_SETUP CPLL_SETUP = {
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.id = PLL_CPLL,
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.conOffset0 = 0x01000000,
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.conOffset1 = 0x01000004,
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.conOffset2 = 0x01000008,
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.conOffset3 = 0x0100000c,
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.modeOffset = 0x01000600,
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.modeShift = 2,
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.lockShift = 10,
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.modeMask = 0x1 << 2,
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.rateTable = PLL_TABLE,
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.minRefdiv = 1,
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.maxRefdiv = 2,
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.minVco = _MHZ(375),
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.maxVco = _MHZ(2400),
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.minFout = _MHZ(24),
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.maxFout = _MHZ(1200),
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.sscgEn = RKX120_SSCG_CPLL_EN,
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};
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static uint32_t RKX12x_HAL_CRU_ClkGetFreq(struct hwclk *hw, uint32_t clockName)
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{
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uint32_t clkMux = CLK_GET_MUX(clockName);
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uint32_t clkDiv = CLK_GET_DIV(clockName);
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uint32_t pRate = 0, freq = 0;
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switch (clockName) {
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case RKX120_CPS_PLL_TXPLL:
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freq = HAL_CRU_GetPllFreq(hw, &TXPLL_SETUP);
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hw->pllRate[RKX120_TXPLL] = freq;
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return freq;
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case RKX120_CPS_PLL_CPLL:
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freq = HAL_CRU_GetPllFreq(hw, &CPLL_SETUP);
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hw->pllRate[RKX120_CPLL] = freq;
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return freq;
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/* link: 300M */
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case RKX120_CPS_E0_CLK_RKLINK_RX_PRE:
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case RKX120_CPS_E1_CLK_RKLINK_RX_PRE:
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/* csi: 50M */
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case RKX120_CPS_CLK_TXESC_CSITX0:
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case RKX120_CPS_CLK_TXESC_CSITX1:
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/* i2s: 600M */
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case RKX120_CPS_CLK_I2S_SRC_RKLINK_RX:
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/* pwm: 100M */
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case RKX120_CPS_CLK_PWM_TX:
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case RKX120_CPS_PCLKOUT_DVPTX:
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freq = HAL_CRU_MuxGetFreq3(hw, clkMux,
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hw->pllRate[RKX120_TXPLL],
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hw->pllRate[RKX120_CPLL], OSC_24M);
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break;
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/* gate clock from TX_E0_CLK_RKLINK_RX_PRE */
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case RKX120_CPS_ICLK_C_CSI0:
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return RKX12x_HAL_CRU_ClkGetFreq(hw, RKX120_CPS_E0_CLK_RKLINK_RX_PRE);
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/* gate clock from TX_E1_CLK_RKLINK_RX_PRE */
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case RKX120_CPS_ICLK_C_CSI1:
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return RKX12x_HAL_CRU_ClkGetFreq(hw, RKX120_CPS_E1_CLK_RKLINK_RX_PRE);
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/* pre-bus: 100M */
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case RKX120_CPS_BUSCLK_TX_PRE0:
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freq = HAL_CRU_MuxGetFreq2(hw, clkMux,
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hw->pllRate[RKX120_TXPLL],
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hw->pllRate[RKX120_CPLL]);
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break;
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/*
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* bus: 100MHZ
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*
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* === TX_BUSCLK_TX_PRE gate children ===
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*
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* pclk_tx_cru
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* pclk_tx_grf
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* pclk_tx_gpio0/1
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* pclk_tx_efuse
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* pclk_mipi_grf_tx0/1
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* pclk_tx_i2c2apb
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* pclk_tx_i2c2apb_debug
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* hclk_dvp_tx
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* pclk_csitx0/1
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* pclk_dsitx
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* pclk_rklink_rx
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* pclk_d_dsi_pattern_gen
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* pclk_lvds{0, 1}_pattern_gen
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* pclk_pcs0/1
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* pclk_pcs{0,1}_ada
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* pclk_mipitxphy0/1
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* pclk_pwm_tx
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* pclk_dft2apb
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*/
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case RKX120_CPS_BUSCLK_TX_PRE:
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pRate = RKX12x_HAL_CRU_ClkGetFreq(hw, RKX120_CPS_BUSCLK_TX_PRE0);
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freq = HAL_CRU_MuxGetFreq2(hw, clkMux, OSC_24M, pRate);
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break;
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/* gpio: 24M */
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case RKX120_CPS_DCLK_TX_GPIO0:
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case RKX120_CPS_DCLK_TX_GPIO1:
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/* efuse: 24M */
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case RKX120_CPS_CLK_TX_EFUSE:
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/* pcs_ada: 24M */
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case RKX120_CPS_CLK_PCS0_ADA:
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case RKX120_CPS_CLK_PCS1_ADA:
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/* capture_pwm: 24M */
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case RKX120_CPS_CLK_CAPTURE_PWM_TX:
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return OSC_24M;
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case RKX120_CPS_CLK_PMA2PCS2LINK_CM:
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return _MHZ(200);
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default:
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CRU_ERR("%s: %s: Unknown clk 0x%08x\n", __func__, hw->name, clockName);
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return HAL_INVAL;
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}
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if (!clkMux && !clkDiv) {
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return 0;
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}
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if (clkDiv) {
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freq /= (HAL_CRU_ClkGetDiv(hw, clkDiv));
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}
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return freq;
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}
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static HAL_Status RKX12x_HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName, uint32_t rate)
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{
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uint32_t clkMux = CLK_GET_MUX(clockName);
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uint32_t clkDiv = CLK_GET_DIV(clockName);
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uint32_t mux = 0, div = 1;
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uint32_t pRate = 0;
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uint32_t maxDiv;
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uint32_t pll;
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uint8_t overMax;
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HAL_Status ret = HAL_OK;
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switch (clockName) {
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case RKX120_CPS_PLL_TXPLL:
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ret = HAL_CRU_SetPllFreq(hw, &TXPLL_SETUP, rate);
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hw->pllRate[RKX120_TXPLL] = rate;
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CRU_MSG("%s: TXPLL set rate: %d\n", hw->name, rate);
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return ret;
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case RKX120_CPS_PLL_CPLL:
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ret = HAL_CRU_SetPllFreq(hw, &CPLL_SETUP, rate);
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hw->pllRate[RKX120_CPLL] = rate;
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CRU_MSG("%s: CPLL set rate: %d\n", hw->name, rate);
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return ret;
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/* link(dclk): Allowed to change PLL rate if need ! */
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case RKX120_CPS_E0_CLK_RKLINK_RX_PRE:
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case RKX120_CPS_E1_CLK_RKLINK_RX_PRE:
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/* i2s */
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case RKX120_CPS_CLK_I2S_SRC_RKLINK_RX:
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maxDiv = CLK_DIV_GET_MAXDIV(clkDiv);
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if (DIV_NO_REM(hw->pllRate[RKX120_TXPLL], rate, maxDiv)) {
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mux = 0;
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pRate = hw->pllRate[RKX120_TXPLL];
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} else if (DIV_NO_REM(hw->pllRate[RKX120_CPLL], rate, maxDiv)) {
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mux = 1;
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pRate = hw->pllRate[RKX120_CPLL];
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} else if (DIV_NO_REM(OSC_24M, rate, maxDiv)) {
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mux = 2;
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pRate = OSC_24M;
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} else {
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if (clockName == RKX120_CPS_CLK_I2S_SRC_RKLINK_RX) {
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pll = RKX120_CPS_PLL_CPLL;
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if (DIV_NO_REM(I2S_122888_BEST_PRATE, rate, maxDiv)) {
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pRate = I2S_122888_BEST_PRATE;
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} else if (DIV_NO_REM(I2S_112896_BEST_PRATE, rate, maxDiv)) {
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pRate = I2S_112896_BEST_PRATE;
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}
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} else {
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pll = RKX120_CPS_PLL_TXPLL;
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}
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/* PLL change closest new rate <= 1200M if need */
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if (!pRate) {
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pRate = (_MHZ(1200) / rate) * rate;
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}
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ret = RKX12x_HAL_CRU_ClkSetFreq(hw, pll, pRate);
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if (ret != HAL_OK) {
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return ret;
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}
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/* if success, continue to set divider */
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}
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break;
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/* csi */
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case RKX120_CPS_CLK_TXESC_CSITX0:
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case RKX120_CPS_CLK_TXESC_CSITX1:
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/* pwm */
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case RKX120_CPS_CLK_PWM_TX:
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case RKX120_CPS_PCLKOUT_DVPTX:
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mux = HAL_CRU_RoundFreqGetMux3(hw, rate,
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hw->pllRate[RKX120_TXPLL],
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hw->pllRate[RKX120_CPLL], OSC_24M, &pRate);
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break;
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/* gate clock from TX_E0_CLK_RKLINK_RX_PRE */
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case RKX120_CPS_ICLK_C_CSI0:
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return RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_E0_CLK_RKLINK_RX_PRE, rate);
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/* gate clock from TX_E1_CLK_RKLINK_RX_PRE */
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case RKX120_CPS_ICLK_C_CSI1:
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return RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_E1_CLK_RKLINK_RX_PRE, rate);
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/* pre-bus */
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case RKX120_CPS_BUSCLK_TX_PRE0:
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mux = HAL_CRU_RoundFreqGetMux2(hw, rate,
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hw->pllRate[RKX120_TXPLL],
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hw->pllRate[RKX120_CPLL], &pRate);
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break;
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case RKX120_CPS_BUSCLK_TX_PRE:
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if (rate == OSC_24M) {
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return HAL_CRU_ClkSetMux(hw, clkMux, 0);
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} else {
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_BUSCLK_TX_PRE0, rate);
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return HAL_CRU_ClkSetMux(hw, clkMux, 1);
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}
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break;
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/* gpio: 24M */
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case RKX120_CPS_DCLK_TX_GPIO0:
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case RKX120_CPS_DCLK_TX_GPIO1:
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/* efuse: 24M */
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case RKX120_CPS_CLK_TX_EFUSE:
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/* pcs_ada: 24M */
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case RKX120_CPS_CLK_PCS0_ADA:
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case RKX120_CPS_CLK_PCS1_ADA:
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/* capture_pwm: 24M */
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case RKX120_CPS_CLK_CAPTURE_PWM_TX:
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return rate == OSC_24M ? 0 : HAL_INVAL;
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case RKX120_CPS_CLK_PMA2PCS2LINK_CM:
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if (rate != _MHZ(200)) {
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return HAL_INVAL;
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}
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HAL_CRU_ClkSetMux(hw, clkMux, 0);
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return HAL_OK;
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default:
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CRU_ERR("%s: %s: Unknown clk 0x%08x\n", __func__, hw->name, clockName);
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return HAL_INVAL;
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}
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if (!clkMux && !clkDiv) {
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return HAL_INVAL;
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}
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if (pRate) {
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div = HAL_DIV_ROUND_UP(pRate, rate);
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}
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if (clkDiv) {
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overMax = div > CLK_DIV_GET_MAXDIV(clkDiv);
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if (overMax) {
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CRU_MSG("%s: %s: Clk '0x%08x' req div(%d) over max(%d)!\n",
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__func__, hw->name, clockName, div, CLK_DIV_GET_MAXDIV(clkDiv));
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div = CLK_DIV_GET_MAXDIV(clkDiv);
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}
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HAL_CRU_ClkSetDiv(hw, clkDiv, div);
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}
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if (clkMux) {
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HAL_CRU_ClkSetMux(hw, clkMux, mux);
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}
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return HAL_OK;
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}
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#if RKX120_SSCG_CPLL_EN || RKX120_SSCG_TXPLL_EN
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static void RKX12x_HAL_CRU_Init_SSCG(struct hwclk *hw)
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{
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uint8_t down_spread = 1; /* 0: center spread */
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uint8_t amplitude = 8; /* range: 0x00 - 0x1f */
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#if RKX120_SSCG_CPLL_EN
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/* down-spread, 0.8%, 37.5khz */
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HAL_CRU_Write(hw, hw->cru_base + 0x0c, 0x1f000000 | ((amplitude & 0x1f) << 8));
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HAL_CRU_Write(hw, hw->cru_base + 0x0c, 0x00f00050);
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HAL_CRU_Write(hw, hw->cru_base + 0x0c, 0x00080000 | ((down_spread & 0x1) << 3));
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HAL_CRU_Write(hw, hw->cru_base + 0x04, 0x10000000);
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HAL_CRU_Write(hw, hw->cru_base + 0x0c, 0x00070000);
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CRU_MSG("%s: CPLL enable SSCG\n", hw->name);
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#endif
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#if RKX120_SSCG_TXPLL_EN
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/* down-spread, 0.8%, 37.5khz */
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HAL_CRU_Write(hw, hw->cru_base + 0x2c, 0x1f000000 | ((amplitude & 0x1f) << 8));
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HAL_CRU_Write(hw, hw->cru_base + 0x2c, 0x00f00050);
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HAL_CRU_Write(hw, hw->cru_base + 0x2c, 0x00080000 | ((down_spread & 0x1) << 3));
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HAL_CRU_Write(hw, hw->cru_base + 0x24, 0x10000000);
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HAL_CRU_Write(hw, hw->cru_base + 0x2c, 0x00070000);
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CRU_MSG("%s: TXPLL enable SSCG\n", hw->name);
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#endif
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}
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#endif
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static HAL_Status RKX12x_HAL_CRU_InitTestout(struct hwclk *hw, uint32_t clockName,
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uint32_t muxValue, uint32_t divValue)
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{
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uint32_t clkMux = CLK_GET_MUX(RKX120_CPS_TEST_CLKOUT);
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uint32_t clkDiv = CLK_GET_DIV(RKX120_CPS_TEST_CLKOUT);
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/* gpio0_b7: iomux to clk_testout */
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HAL_CRU_Write(hw, RKX120_GRF_GPIO0B_IOMUX_H, GPIO0B7_TEST_CLKOUT);
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/* Enable clock */
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HAL_CRU_ClkEnable(hw, RKX120_CLK_TESTOUT_TOP_GATE);
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/* Mux, div */
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HAL_CRU_ClkSetDiv(hw, clkDiv, divValue);
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HAL_CRU_ClkSetMux(hw, clkMux, muxValue);
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CRU_MSG("%s: Testout div=%d, mux=%d\n", hw->name, divValue, muxValue);
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return HAL_OK;
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}
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static HAL_Status RKX12x_HAL_CRU_Init(struct hwclk *hw, struct xferclk *xfer)
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{
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hw->cru_base = 0x01000000;
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hw->sel_con0 = hw->cru_base + 0x100;
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hw->gate_con0 = hw->cru_base + 0x300;
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hw->softrst_con0 = hw->cru_base + 0x400;
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hw->gbl_srst_fst = 0x0614;
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hw->flags = 0;
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hw->num_gate = 16 * 12;
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hw->gate = HAL_KCALLOC(hw->num_gate, sizeof(struct clkGate));
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if (!hw->gate) {
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return HAL_NOMEM;
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}
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strcat(hw->name, "<CRU.120@");
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strcat(hw->name, xfer->name);
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strcat(hw->name, ">");
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/* Don't change order */
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#if RKX120_SSCG_CPLL_EN || RKX120_SSCG_TXPLL_EN
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RKX12x_HAL_CRU_Init_SSCG(hw);
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#endif
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_PLL_CPLL, _MHZ(1200));
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_PLL_TXPLL, _MHZ(1188));
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_BUSCLK_TX_PRE, _MHZ(24));
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_CLK_PMA2PCS2LINK_CM, _MHZ(200));
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_CLK_I2S_SRC_RKLINK_RX, _MHZ(300));
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_CLK_PWM_TX, _MHZ(24));
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_CLK_TXESC_CSITX0, _MHZ(20));
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_CLK_TXESC_CSITX1, _MHZ(20));
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/* Must be the same rate as RKX110_CPS_DCLK_RX_PRE when camera mode */
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_E0_CLK_RKLINK_RX_PRE, _MHZ(200));
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RKX12x_HAL_CRU_ClkSetFreq(hw, RKX120_CPS_E1_CLK_RKLINK_RX_PRE, _MHZ(200));
|
|
HAL_CRU_ClkEnable(hw, RKX120_CLK_TESTOUT_TOP_GATE);
|
|
#if RKX120_TESTOUT_MUX >= 0
|
/* clk_testout support max 150M output, so set div=10 by default if not 24M */
|
RKX12x_HAL_CRU_InitTestout(hw, RKX120_CPS_TEST_CLKOUT, RKX120_TESTOUT_MUX,
|
RKX120_TESTOUT_MUX == 0 ? 1 : 10);
|
#endif
|
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return HAL_OK;
|
}
|
|
PNAME(mux_24m_p) = { "xin24m" };
|
PNAME(mux_txpll_cpll_p) = { "txpll", "cpll" };
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PNAME(mux_txpll_cpll_24m_p) = { "txpll", "cpll", "xin24m" };
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PNAME(mux_24m_txpre0_p) = { "xin24m", "busclk_tx_pre0" };
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#define CAL_FREQ_REG 0x01000f00
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static uint32_t RKX12x_HAL_CRU_ClkGetExtFreq(struct hwclk *hw, uint32_t clk)
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{
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uint32_t clkMux = CLK_GET_MUX(RKX120_CPS_TEST_CLKOUT);
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uint32_t clkDiv = CLK_GET_DIV(RKX120_CPS_TEST_CLKOUT);
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uint32_t freq, mhz;
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uint8_t div = 10;
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HAL_CRU_ClkSetDiv(hw, clkDiv, div);
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HAL_CRU_ClkSetMux(hw, clkMux, 0);
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HAL_SleepMs(2);
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HAL_CRU_ClkSetMux(hw, clkMux, clk);
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HAL_SleepMs(2);
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freq = HAL_CRU_Read(hw, CAL_FREQ_REG);
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/* Fix accuracy */
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if ((freq % 10) == 0x9) {
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freq++;
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}
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freq *= (1000 * div);
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/* If no external input, freq is close to 24M */
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mhz = freq / 1000000;
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if ((clk != 0) && (mhz == 23 || mhz == 24)) {
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freq = 0;
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}
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return freq;
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}
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static struct clkTable rkx12x_clkTable[] = {
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/* internal */
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CLK_DECLARE_INT("txpll", RKX120_CPS_PLL_TXPLL, mux_24m_p),
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CLK_DECLARE_INT("cpll", RKX120_CPS_PLL_CPLL, mux_24m_p),
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CLK_DECLARE_INT("e0_clk_rklink_rx_pre", RKX120_CPS_E0_CLK_RKLINK_RX_PRE, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("e1_clk_rklink_rx_pre", RKX120_CPS_E1_CLK_RKLINK_RX_PRE, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("iclk_c_csi0", RKX120_CPS_ICLK_C_CSI0, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("iclk_c_csi1", RKX120_CPS_ICLK_C_CSI1, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("clk_txesc_csitx0", RKX120_CPS_CLK_TXESC_CSITX0, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("clk_txesc_csitx1", RKX120_CPS_CLK_TXESC_CSITX1, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("clk_i2s_src_rklink_rx", RKX120_CPS_CLK_I2S_SRC_RKLINK_RX, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("clk_pwm_tx", RKX120_CPS_CLK_PWM_TX, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("pclkout_dvptx", RKX120_CPS_PCLKOUT_DVPTX, mux_txpll_cpll_24m_p),
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CLK_DECLARE_INT("busclk_tx_pre0", RKX120_CPS_BUSCLK_TX_PRE0, mux_txpll_cpll_p),
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CLK_DECLARE_INT("busclk_tx_pre", RKX120_CPS_BUSCLK_TX_PRE, mux_24m_txpre0_p),
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CLK_DECLARE_INT("dclk_tx_gpio0", RKX120_CPS_DCLK_TX_GPIO0, mux_24m_p),
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CLK_DECLARE_INT("dclk_tx_gpio1", RKX120_CPS_DCLK_TX_GPIO1, mux_24m_p),
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CLK_DECLARE_INT("clk_tx_efuse", RKX120_CPS_CLK_TX_EFUSE, mux_24m_p),
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CLK_DECLARE_INT("clk_pcs0_ada", RKX120_CPS_CLK_PCS0_ADA, mux_24m_p),
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CLK_DECLARE_INT("clk_pcs1_ada", RKX120_CPS_CLK_PCS1_ADA, mux_24m_p),
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CLK_DECLARE_INT("clk_capture_pwm_tx", RKX120_CPS_CLK_CAPTURE_PWM_TX, mux_24m_p),
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/* external */
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CLK_DECLARE_EXT("xin24m", 0, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_txbytehs_csitx0", 3, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_txbytehs_csitx1", 5, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_txbytehs_dsitx", 7, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_rxesc_dsitx", 8, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_link_pcs0", 9, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_link_pcs1", 10, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_pmarx0_pixel", 11, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_pmarx1_pixel", 12, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_mipitxphy0_lvds", 13, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_mipitxphy0_pixel", 14, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_mipitxphy1_lvds", 15, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_mipitxphy1_pixel", 16, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_txbytehs_dsitx_csitx0", 23, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("dclk_c_dvp_src", 24, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("dclk_d_dsi_src", 25, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_lvds0_src", 26, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_lvds1_src", 27, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("dclk_rgb_src", 28, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_2x_pma2pcs0", 29, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_2x_pma2pcs1", 30, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT("clk_txesc_mipitxphy0", 31, RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("dclk_d_ds", 25, "dclk_d_dsi_src", RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("dclk_d_dsi_pattern_gen", 25, "dclk_d_dsi_src", RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("clk_lvds0", 26, "clk_lvds0_src", RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("clk_lvds0_pattern_gen", 26, "clk_lvds0_src", RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("clk_lvds1", 27, "clk_lvds1_src", RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("clk_lvds1_pattern_gen", 27, "clk_lvds1_src", RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("clk_pma2pcs0", 9, "clk_link_pcs0", RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("clk_pma2link2pcs_cm", 9, "clk_link_pcs0", RKX12x_HAL_CRU_ClkGetExtFreq),
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CLK_DECLARE_EXT_PARENT("clk_pma2pcs1", 10, "clk_link_pcs1", RKX12x_HAL_CRU_ClkGetExtFreq),
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|
{ /* sentinel */ },
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};
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struct clkOps rkx120_clk_ops =
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{
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.clkTable = rkx12x_clkTable,
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.clkInit = RKX12x_HAL_CRU_Init,
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.clkGetFreq = RKX12x_HAL_CRU_ClkGetFreq,
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.clkSetFreq = RKX12x_HAL_CRU_ClkSetFreq,
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.clkInitTestout = RKX12x_HAL_CRU_InitTestout,
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};
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