/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Rockchip Electronics Co. Ltd.
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*
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* Author: Joseph Chen <chenjh@rock-chips.com>
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*/
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#ifndef _CRU_API_H_
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#define _CRU_API_H_
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#include "hal_def.h"
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#include "hal_os_def.h"
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#include "cru_core.h"
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#include "cru_rkx110.h"
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#include "cru_rkx120.h"
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#include "cru_rkx111.h"
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#include "cru_rkx121.h"
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static HAL_DEFINE_MUTEX(top_lock);
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static inline bool hwclk_is_enabled(struct hwclk *hw, uint32_t clk)
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{
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bool ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkIsEnabled(hw, clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline int hwclk_enable(struct hwclk *hw, uint32_t clk)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkEnable(hw, clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline int hwclk_disable(struct hwclk *hw, uint32_t clk)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkDisable(hw, clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline bool hwclk_is_reset(struct hwclk *hw, uint32_t clk)
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{
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bool ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkIsReset(hw, clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline int hwclk_reset(struct hwclk *hw, uint32_t clk)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkResetAssert(hw, clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline int hwclk_reset_deassert(struct hwclk *hw, uint32_t clk)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkResetDeassert(hw, clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline int hwclk_set_div(struct hwclk *hw, uint32_t clk, uint32_t div)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkSetDiv(hw, clk, div);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline uint32_t hwclk_get_div(struct hwclk *hw, uint32_t clk)
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{
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uint32_t ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkGetDiv(hw, clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline int hwclk_set_mux(struct hwclk *hw, uint32_t clk, uint32_t mux)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkSetMux(hw, clk, mux);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline uint32_t hwclk_get_mux(struct hwclk *hw, uint32_t clk)
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{
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uint32_t ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkGetMux(hw, clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline uint32_t hwclk_get_rate(struct hwclk *hw, uint32_t composite_clk)
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{
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uint32_t ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkGetFreq(hw, composite_clk);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline int hwclk_set_rate(struct hwclk *hw, uint32_t composite_clk, uint32_t rate)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkSetFreq(hw, composite_clk, rate);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline int hwclk_set_testout(struct hwclk *hw, uint32_t composite_clk,
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uint32_t mux, uint32_t div)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_ClkSetTestout(hw, composite_clk, mux, div);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline void hwclk_dump_tree(HAL_ClockType type)
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{
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HAL_MutexLock(&top_lock);
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HAL_CRU_ClkDumpTree(type);
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HAL_MutexUnlock(&top_lock);
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}
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static inline int hwclk_set_glbsrst(struct hwclk *hw, uint32_t type)
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{
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int ret;
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HAL_MutexLock(&hw->lock);
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ret = HAL_CRU_SetGlbSrst(hw, type);
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HAL_MutexUnlock(&hw->lock);
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return ret;
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}
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static inline struct hwclk *hwclk_register(struct xferclk xfer)
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{
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struct hwclk *ret;
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HAL_MutexLock(&top_lock);
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ret = HAL_CRU_Register(xfer);
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HAL_MutexUnlock(&top_lock);
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return ret;
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}
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static inline struct hwclk *hwclk_get(void *client)
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{
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struct hwclk *ret;
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HAL_MutexLock(&top_lock);
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ret = HAL_CRU_ClkGet(client);
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HAL_MutexUnlock(&top_lock);
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return ret;
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}
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static inline int hwclk_init(void)
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{
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return HAL_CRU_Init();
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}
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#endif
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