// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* maxim-bu18rl82.c -- I2C register interface access for bu18rl82 serdes chip
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*
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* Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd.
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*
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* Author: luowei <lw@rock-chips.com>
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*/
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#include "../core.h"
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#include "rohm-bu18rl82.h"
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#define PINCTRL_GROUP(a, b, c) { .name = a, .pins = b, .num_pins = c}
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static bool bu18rl82_volatile_reg(struct device *dev, unsigned int reg)
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{
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return true;
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}
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static struct regmap_config bu18rl82_regmap_config = {
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.name = "bu18rl82",
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0x0700,
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.volatile_reg = bu18rl82_volatile_reg,
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.cache_type = REGCACHE_RBTREE,
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};
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static int BU18RL82_GPIO0_pins[] = {0};
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static int BU18RL82_GPIO1_pins[] = {1};
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static int BU18RL82_GPIO2_pins[] = {2};
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static int BU18RL82_GPIO3_pins[] = {3};
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static int BU18RL82_GPIO4_pins[] = {4};
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static int BU18RL82_GPIO5_pins[] = {5};
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static int BU18RL82_GPIO6_pins[] = {6};
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static int BU18RL82_GPIO7_pins[] = {7};
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#define GROUP_DESC(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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}
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struct serdes_function_data {
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u8 gpio_rx_en:1;
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u16 gpio_id;
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};
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static const char *serdes_gpio_groups[] = {
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"BU18RL82_GPIO0", "BU18RL82_GPIO1", "BU18RL82_GPIO2", "BU18RL82_GPIO3",
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"BU18RL82_GPIO4", "BU18RL82_GPIO5", "BU18RL82_GPIO6", "BU18RL82_GPIO7",
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};
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/*des -> ser -> soc*/
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#define FUNCTION_DESC_GPIO_INPUT(id) \
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{ \
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.name = "DES_TO_SER_GPIO"#id, \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_rx_en = 1, .gpio_id = id + 2 } \
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}, \
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} \
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/*soc -> ser -> des*/
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#define FUNCTION_DESC_GPIO_OUTPUT(id) \
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{ \
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.name = "SER_GPIO"#id"_TO_DES", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_rx_en = 0, .gpio_id = id + 2 } \
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}, \
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} \
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/*des -> device*/
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#define FUNCTION_DESC_GPIO_OUTPUT_HIGH() \
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{ \
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.name = "DES_GPIO_OUTPUT_HIGH", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_rx_en = 0, .gpio_id = 1 } \
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}, \
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} \
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#define FUNCTION_DESC_GPIO_OUTPUT_LOW() \
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{ \
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.name = "DES_GPIO_OUTPUT_LOW", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_rx_en = 0, .gpio_id = 0 } \
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}, \
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} \
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static struct pinctrl_pin_desc bu18rl82_pins_desc[] = {
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PINCTRL_PIN(ROHM_BU18RL82_GPIO0, "BU18RL82_GPIO0"),
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PINCTRL_PIN(ROHM_BU18RL82_GPIO1, "BU18RL82_GPIO1"),
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PINCTRL_PIN(ROHM_BU18RL82_GPIO2, "BU18RL82_GPIO2"),
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PINCTRL_PIN(ROHM_BU18RL82_GPIO3, "BU18RL82_GPIO3"),
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PINCTRL_PIN(ROHM_BU18RL82_GPIO4, "BU18RL82_GPIO4"),
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PINCTRL_PIN(ROHM_BU18RL82_GPIO5, "BU18RL82_GPIO5"),
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PINCTRL_PIN(ROHM_BU18RL82_GPIO6, "BU18RL82_GPIO6"),
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PINCTRL_PIN(ROHM_BU18RL82_GPIO7, "BU18RL82_GPIO7"),
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};
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static struct group_desc bu18rl82_groups_desc[] = {
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GROUP_DESC(BU18RL82_GPIO0),
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GROUP_DESC(BU18RL82_GPIO1),
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GROUP_DESC(BU18RL82_GPIO2),
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GROUP_DESC(BU18RL82_GPIO3),
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GROUP_DESC(BU18RL82_GPIO4),
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GROUP_DESC(BU18RL82_GPIO5),
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GROUP_DESC(BU18RL82_GPIO6),
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GROUP_DESC(BU18RL82_GPIO7),
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};
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static struct function_desc bu18rl82_functions_desc[] = {
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FUNCTION_DESC_GPIO_INPUT(0),
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FUNCTION_DESC_GPIO_INPUT(1),
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FUNCTION_DESC_GPIO_INPUT(2),
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FUNCTION_DESC_GPIO_INPUT(3),
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FUNCTION_DESC_GPIO_INPUT(4),
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FUNCTION_DESC_GPIO_INPUT(5),
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FUNCTION_DESC_GPIO_INPUT(6),
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FUNCTION_DESC_GPIO_INPUT(7),
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FUNCTION_DESC_GPIO_INPUT(8),
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FUNCTION_DESC_GPIO_INPUT(9),
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FUNCTION_DESC_GPIO_INPUT(10),
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FUNCTION_DESC_GPIO_INPUT(11),
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FUNCTION_DESC_GPIO_INPUT(12),
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FUNCTION_DESC_GPIO_INPUT(13),
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FUNCTION_DESC_GPIO_INPUT(14),
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FUNCTION_DESC_GPIO_INPUT(15),
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FUNCTION_DESC_GPIO_OUTPUT(0),
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FUNCTION_DESC_GPIO_OUTPUT(1),
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FUNCTION_DESC_GPIO_OUTPUT(2),
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FUNCTION_DESC_GPIO_OUTPUT(3),
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FUNCTION_DESC_GPIO_OUTPUT(4),
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FUNCTION_DESC_GPIO_OUTPUT(5),
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FUNCTION_DESC_GPIO_OUTPUT(6),
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FUNCTION_DESC_GPIO_OUTPUT(7),
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FUNCTION_DESC_GPIO_OUTPUT(8),
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FUNCTION_DESC_GPIO_OUTPUT(9),
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FUNCTION_DESC_GPIO_OUTPUT(10),
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FUNCTION_DESC_GPIO_OUTPUT(11),
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FUNCTION_DESC_GPIO_OUTPUT(12),
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FUNCTION_DESC_GPIO_OUTPUT(13),
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FUNCTION_DESC_GPIO_OUTPUT(14),
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FUNCTION_DESC_GPIO_OUTPUT(15),
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FUNCTION_DESC_GPIO_OUTPUT_HIGH(),
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FUNCTION_DESC_GPIO_OUTPUT_LOW(),
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};
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static struct serdes_chip_pinctrl_info bu18rl82_pinctrl_info = {
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.pins = bu18rl82_pins_desc,
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.num_pins = ARRAY_SIZE(bu18rl82_pins_desc),
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.groups = bu18rl82_groups_desc,
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.num_groups = ARRAY_SIZE(bu18rl82_groups_desc),
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.functions = bu18rl82_functions_desc,
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.num_functions = ARRAY_SIZE(bu18rl82_functions_desc),
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};
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static void bu18rl82_bridge_swrst(struct serdes *serdes)
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{
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struct device *dev = serdes->dev;
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int ret;
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ret = serdes_reg_write(serdes, BU18RL82_REG_RESET, BIT(0) | BIT(1) | BIT(7));
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if (ret < 0)
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dev_err(dev, "%s: failed to reset bu18rl82 0x11 ret=%d\n", __func__, ret);
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mdelay(20);
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SERDES_DBG_CHIP("%s: serdes %s ret=%d\n", __func__, serdes->chip_data->name, ret);
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}
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static void bu18rl82_enable_hwint(struct serdes *serdes, int enable)
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{
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struct device *dev = serdes->dev;
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int i, ret;
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for (i = 0; i < ARRAY_SIZE(bu18rl82_reg_ien); i++) {
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if (enable) {
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ret = serdes_reg_write(serdes, bu18rl82_reg_ien[i].reg,
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bu18rl82_reg_ien[i].ien);
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if (ret)
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dev_err(dev, "reg 0x%04x write error\n", bu18rl82_reg_ien[i].reg);
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} else {
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ret = serdes_reg_write(serdes, bu18rl82_reg_ien[i].reg, 0);
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if (ret)
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dev_err(dev, "reg 0x%04x write error\n", bu18rl82_reg_ien[i].reg);
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}
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}
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SERDES_DBG_CHIP("%s: serdes %s ret=%d\n", __func__,
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serdes->chip_data->name, enable);
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}
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static int bu18rl82_bridge_init(struct serdes *serdes)
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{
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return 0;
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bu18rl82_bridge_swrst(serdes);
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return 0;
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}
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static int bu18rl82_bridge_enable(struct serdes *serdes)
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{
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int ret = 0;
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/* 1:enable 0:disable */
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bu18rl82_enable_hwint(serdes, 0);
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SERDES_DBG_CHIP("%s: serdes %s ret=%d\n", __func__,
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serdes->chip_data->name, ret);
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return ret;
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}
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static int bu18rl82_bridge_disable(struct serdes *serdes)
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{
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return 0;
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}
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static struct serdes_chip_bridge_ops bu18rl82_bridge_ops = {
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.init = bu18rl82_bridge_init,
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.enable = bu18rl82_bridge_enable,
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.disable = bu18rl82_bridge_disable,
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};
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static int bu18rl82_pinctrl_config_get(struct serdes *serdes,
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unsigned int pin, unsigned long *config)
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{
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enum pin_config_param param = pinconf_to_config_param(*config);
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unsigned int bu18rl82_gpio_sw_reg, bu18rl82_gpio_pden_reg, bu18rl82_gpio_oen_reg;
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u16 arg = 0;
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serdes_reg_read(serdes, bu18rl82_gpio_sw[pin].reg, &bu18rl82_gpio_sw_reg);
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serdes_reg_read(serdes, bu18rl82_gpio_pden[pin].reg, &bu18rl82_gpio_pden_reg);
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serdes_reg_read(serdes, bu18rl82_gpio_oen[pin].reg, &bu18rl82_gpio_oen_reg);
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SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n",
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__func__, serdes->chip_data->name, pin, param);
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switch (param) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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arg = FIELD_GET(BIT(2) | BIT(1), bu18rl82_gpio_sw_reg);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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arg = FIELD_GET(BIT(4), bu18rl82_gpio_pden_reg);
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break;
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case PIN_CONFIG_OUTPUT:
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arg = FIELD_GET(BIT(3), bu18rl82_gpio_oen_reg);
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break;
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default:
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return -EOPNOTSUPP;
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}
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*config = pinconf_to_config_packed(param, arg);
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SERDES_DBG_CHIP("%s: serdes chip %s pin=%d arg=%d\n",
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__func__, serdes->chip_data->name, pin, arg);
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return 0;
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}
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static int bu18rl82_pinctrl_config_set(struct serdes *serdes,
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unsigned int pin, unsigned long *configs,
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unsigned int num_configs)
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{
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enum pin_config_param param;
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u32 arg;
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int i;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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serdes_set_bits(serdes, bu18rl82_gpio_sw[pin].reg,
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bu18rl82_gpio_sw[pin].mask,
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FIELD_PREP(BIT(2) | BIT(1), arg));
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SERDES_DBG_CHIP("%s: serdes chip %s pin=%d i=%d drive-strength arg=0x%x\n",
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__func__, serdes->chip_data->name, pin, i, arg);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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serdes_set_bits(serdes, bu18rl82_gpio_pden[pin].reg,
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bu18rl82_gpio_pden[i].mask,
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FIELD_PREP(BIT(4), arg));
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SERDES_DBG_CHIP("%s: serdes chip %s pin=%d i=%d pull-down arg=0x%x\n",
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__func__, serdes->chip_data->name, pin, i, arg);
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break;
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break;
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case PIN_CONFIG_OUTPUT:
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serdes_set_bits(serdes, bu18rl82_gpio_oen[pin].reg,
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bu18rl82_gpio_oen[i].mask,
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FIELD_PREP(BIT(3), arg));
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SERDES_DBG_CHIP("%s: serdes chip %s pin=%d i=%d output arg=0x%x\n",
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__func__, serdes->chip_data->name, pin, i, arg);
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break;
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default:
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return -EOPNOTSUPP;
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}
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}
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return 0;
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}
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static int bu18rl82_pinctrl_set_mux(struct serdes *serdes,
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unsigned int function, unsigned int group)
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{
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struct serdes_pinctrl *pinctrl = serdes->pinctrl;
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struct function_desc *func;
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struct group_desc *grp;
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int i, offset;
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func = pinmux_generic_get_function(pinctrl->pctl, function);
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if (!func)
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return -EINVAL;
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grp = pinctrl_generic_get_group(pinctrl->pctl, group);
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if (!grp)
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return -EINVAL;
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SERDES_DBG_CHIP("%s: serdes chip %s func=%s data=%p group=%s data=%p, num_pin=%d\n",
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__func__, serdes->chip_data->name, func->name,
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func->data, grp->name, grp->data, grp->num_pins);
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if (func->data) {
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struct serdes_function_data *fdata = func->data;
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for (i = 0; i < grp->num_pins; i++) {
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offset = grp->pins[i] - pinctrl->pin_base;
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if (offset > 7)
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dev_err(serdes->dev, "%s gpio offset=%d too large > 7\n",
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serdes->chip_data->name, offset);
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else
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SERDES_DBG_CHIP("%s: serdes chip %s gpio_id=0x%x, offset=%d\n",
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__func__, serdes->chip_data->name, fdata->gpio_id, offset);
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serdes_set_bits(serdes, bu18rl82_gpio_oen[offset].reg,
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bu18rl82_gpio_oen[offset].mask,
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FIELD_PREP(BIT(3), fdata->gpio_rx_en));
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serdes_set_bits(serdes, bu18rl82_gpio_id_low[offset].reg,
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bu18rl82_gpio_id_low[offset].mask,
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FIELD_PREP(GENMASK(7, 0),
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(fdata->gpio_id & 0xff)));
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serdes_set_bits(serdes, bu18rl82_gpio_id_high[offset].reg,
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bu18rl82_gpio_id_high[offset].mask,
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FIELD_PREP(GENMASK(2, 0),
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((fdata->gpio_id >> 8) & 0x7)));
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serdes_set_bits(serdes, bu18rl82_gpio_pden[offset].reg,
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bu18rl82_gpio_pden[offset].mask,
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FIELD_PREP(BIT(4), 0));
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}
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}
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return 0;
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}
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static struct serdes_chip_pinctrl_ops bu18rl82_pinctrl_ops = {
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.pin_config_get = bu18rl82_pinctrl_config_get,
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.pin_config_set = bu18rl82_pinctrl_config_set,
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.set_mux = bu18rl82_pinctrl_set_mux,
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};
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static int bu18rl82_gpio_direction_input(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static int bu18rl82_gpio_direction_output(struct serdes *serdes, int gpio, int value)
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{
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return 0;
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}
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static int bu18rl82_gpio_get_level(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static int bu18rl82_gpio_set_level(struct serdes *serdes, int gpio, int value)
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{
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return 0;
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}
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static int bu18rl82_gpio_set_config(struct serdes *serdes, int gpio, unsigned long config)
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{
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return 0;
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}
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static int bu18rl82_gpio_to_irq(struct serdes *serdes, int gpio)
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{
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return 0;
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}
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static struct serdes_chip_gpio_ops bu18rl82_gpio_ops = {
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.direction_input = bu18rl82_gpio_direction_input,
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.direction_output = bu18rl82_gpio_direction_output,
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.get_level = bu18rl82_gpio_get_level,
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.set_level = bu18rl82_gpio_set_level,
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.set_config = bu18rl82_gpio_set_config,
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.to_irq = bu18rl82_gpio_to_irq,
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};
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static int bu18rl82_pm_suspend(struct serdes *serdes)
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{
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return 0;
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}
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static int bu18rl82_pm_resume(struct serdes *serdes)
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{
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return 0;
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}
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static struct serdes_chip_pm_ops bu18rl82_pm_ops = {
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.suspend = bu18rl82_pm_suspend,
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.resume = bu18rl82_pm_resume,
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};
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static int bu18rl82_irq_lock_handle(struct serdes *serdes)
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{
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return IRQ_HANDLED;
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}
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static int bu18rl82_irq_err_handle(struct serdes *serdes)
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{
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return IRQ_HANDLED;
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}
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static struct serdes_chip_irq_ops bu18rl82_irq_ops = {
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.lock_handle = bu18rl82_irq_lock_handle,
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.err_handle = bu18rl82_irq_err_handle,
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};
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struct serdes_chip_data serdes_bu18rl82_data = {
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.name = "bu18rl82",
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.serdes_type = TYPE_DES,
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.serdes_id = ROHM_ID_BU18RL82,
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.bridge_type = TYPE_BRIDGE_BRIDGE,
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.connector_type = DRM_MODE_CONNECTOR_LVDS,
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.regmap_config = &bu18rl82_regmap_config,
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.pinctrl_info = &bu18rl82_pinctrl_info,
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.bridge_ops = &bu18rl82_bridge_ops,
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.pinctrl_ops = &bu18rl82_pinctrl_ops,
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.gpio_ops = &bu18rl82_gpio_ops,
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.pm_ops = &bu18rl82_pm_ops,
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.irq_ops = &bu18rl82_irq_ops,
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};
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EXPORT_SYMBOL_GPL(serdes_bu18rl82_data);
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MODULE_LICENSE("GPL");
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