// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* maxim-max96755.c -- I2C register interface access for max96755 serdes chip
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*
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* Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd.
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*
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* Author:
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*/
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#include "../core.h"
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#include "maxim-max96755.h"
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static bool max96755_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case 0x0002:
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case 0x0010:
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case 0x0013:
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case 0x0053:
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case 0x0057:
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case 0x02be ... 0x02fc:
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case 0x0311:
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case 0x032a:
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case 0x0330 ... 0x0331:
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case 0x0385 ... 0x0387:
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case 0x03a4 ... 0x03ae:
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return false;
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default:
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return true;
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}
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}
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static struct regmap_config max96755_regmap_config = {
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.name = "max96755",
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0x8000,
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.volatile_reg = max96755_volatile_reg,
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.cache_type = REGCACHE_RBTREE,
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};
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struct serdes_function_data {
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u8 gpio_out_dis:1;
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u8 gpio_tx_en:1;
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u8 gpio_rx_en:1;
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u8 gpio_tx_id;
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u8 gpio_rx_id;
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};
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struct config_desc {
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u16 reg;
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u8 mask;
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u8 val;
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};
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struct serdes_group_data {
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const struct config_desc *configs;
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int num_configs;
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};
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static int MAX96755_MFP0_pins[] = {0};
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static int MAX96755_MFP1_pins[] = {1};
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static int MAX96755_MFP2_pins[] = {2};
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static int MAX96755_MFP3_pins[] = {3};
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static int MAX96755_MFP4_pins[] = {4};
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static int MAX96755_MFP5_pins[] = {5};
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static int MAX96755_MFP6_pins[] = {6};
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static int MAX96755_MFP7_pins[] = {7};
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static int MAX96755_MFP8_pins[] = {8};
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static int MAX96755_MFP9_pins[] = {9};
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static int MAX96755_MFP10_pins[] = {10};
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static int MAX96755_MFP11_pins[] = {11};
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static int MAX96755_MFP12_pins[] = {12};
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static int MAX96755_MFP13_pins[] = {13};
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static int MAX96755_MFP14_pins[] = {14};
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static int MAX96755_MFP15_pins[] = {15};
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static int MAX96755_MFP16_pins[] = {16};
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static int MAX96755_MFP17_pins[] = {17};
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static int MAX96755_MFP18_pins[] = {18};
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static int MAX96755_MFP19_pins[] = {19};
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static int MAX96755_MFP20_pins[] = {20};
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static int MAX96755_I2C_pins[] = {19, 20};
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static int MAX96755_UART_pins[] = {19, 20};
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#define GROUP_DESC(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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}
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#define GROUP_DESC_CONFIG(nm) \
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{ \
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.name = #nm, \
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.pins = nm ## _pins, \
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.num_pins = ARRAY_SIZE(nm ## _pins), \
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.data = (void *)(const struct serdes_group_data []) { \
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{ \
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.configs = nm ## _configs, \
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.num_configs = ARRAY_SIZE(nm ## _configs), \
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} \
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}, \
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}
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static const struct config_desc MAX96755_MFP0_configs[] = {
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{ 0x0005, LOCK_EN, 0 },
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{ 0x0048, LOC_MS_EN, 0 },
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};
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static const struct config_desc MAX96755_MFP1_configs[] = {
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{ 0x0005, ERRB_EN, 0 },
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};
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static const struct config_desc MAX96755_MFP4_configs[] = {
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{ 0x070, SPI_EN, 0 },
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};
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static const struct config_desc MAX96755_MFP5_configs[] = {
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{ 0x006, RCLKEN, 0 },
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};
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static const struct config_desc MAX96755_MFP7_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc MAX96755_MFP8_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc MAX96755_MFP9_configs[] = {
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{ 0x0002, AUD_TX_EN_X, 0 },
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{ 0x0002, AUD_TX_EN_Y, 0 }
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};
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static const struct config_desc MAX96755_MFP10_configs[] = {
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{ 0x0001, IIC_2_EN, 0 },
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{ 0x0003, UART_2_EN, 0 },
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{ 0x0140, AUD_RX_EN, 0 },
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};
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static const struct config_desc MAX96755_MFP11_configs[] = {
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{ 0x0001, IIC_2_EN, 0 },
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{ 0x0003, UART_2_EN, 0 },
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{ 0x0140, AUD_RX_EN, 0 },
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};
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static const struct config_desc MAX96755_MFP12_configs[] = {
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{ 0x0140, AUD_RX_EN, 0 },
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};
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static const struct config_desc MAX96755_MFP13_configs[] = {
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{ 0x0005, PU_LF0, 0 },
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};
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static const struct config_desc MAX96755_MFP14_configs[] = {
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{ 0x0005, PU_LF1, 0 },
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};
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static const struct config_desc MAX96755_MFP15_configs[] = {
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{ 0x0005, PU_LF2, 0 },
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};
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static const struct config_desc MAX96755_MFP16_configs[] = {
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{ 0x0005, PU_LF3, 0 },
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};
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static const struct config_desc MAX96755_MFP17_configs[] = {
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{ 0x0001, IIC_1_EN, 0 },
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{ 0x0003, UART_1_EN, 0 },
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};
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static const struct config_desc MAX96755_MFP18_configs[] = {
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{ 0x0001, IIC_1_EN, 0 },
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{ 0x0003, UART_1_EN, 0 },
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};
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static const char *serdes_gpio_groups[] = {
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"MAX96755_MFP0", "MAX96755_MFP1", "MAX96755_MFP2", "MAX96755_MFP3",
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"MAX96755_MFP4", "MAX96755_MFP5", "MAX96755_MFP6", "MAX96755_MFP7",
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"MAX96755_MFP8", "MAX96755_MFP9", "MAX96755_MFP10", "MAX96755_MFP11",
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"MAX96755_MFP12", "MAX96755_MFP13", "MAX96755_MFP14", "MAX96755_MFP15",
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"MAX96755_MFP16", "MAX96755_MFP17", "MAX96755_MFP18", "MAX96755_MFP19",
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"MAX96755_MFP20",
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};
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static const char *MAX96755_I2C_groups[] = { "MAX96755_I2C" };
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static const char *MAX96755_UART_groups[] = { "MAX96755_UART" };
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#define FUNCTION_DESC(nm) \
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{ \
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.name = #nm, \
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.group_names = nm##_groups, \
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.num_group_names = ARRAY_SIZE(nm##_groups), \
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} \
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#define FUNCTION_DESC_GPIO_INPUT(id) \
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{ \
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.name = "DES_GPIO"#id"_INPUT", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_rx_en = 1, .gpio_rx_id = id } \
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}, \
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} \
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#define FUNCTION_DESC_GPIO_OUTPUT(id) \
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{ \
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.name = "DES_GPIO"#id"_OUTPUT", \
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.group_names = serdes_gpio_groups, \
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.num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
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.data = (void *)(const struct serdes_function_data []) { \
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{ .gpio_out_dis = 1, .gpio_tx_en = 1, .gpio_tx_id = id } \
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}, \
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} \
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static struct pinctrl_pin_desc max96755_pins_desc[] = {
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PINCTRL_PIN(MAXIM_MAX96755_MFP0, "MAX96755_MFP0"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP1, "MAX96755_MFP1"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP2, "MAX96755_MFP2"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP3, "MAX96755_MFP3"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP4, "MAX96755_MFP4"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP5, "MAX96755_MFP5"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP6, "MAX96755_MFP6"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP7, "MAX96755_MFP7"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP8, "MAX96755_MFP8"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP9, "MAX96755_MFP9"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP10, "MAX96755_MFP10"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP11, "MAX96755_MFP11"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP12, "MAX96755_MFP12"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP13, "MAX96755_MFP13"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP14, "MAX96755_MFP14"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP15, "MAX96755_MFP15"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP16, "MAX96755_MFP16"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP17, "MAX96755_MFP17"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP18, "MAX96755_MFP18"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP19, "MAX96755_MFP19"),
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PINCTRL_PIN(MAXIM_MAX96755_MFP20, "MAX96755_MFP20"),
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};
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static struct group_desc max96755_groups_desc[] = {
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GROUP_DESC_CONFIG(MAX96755_MFP0),
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GROUP_DESC_CONFIG(MAX96755_MFP1),
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GROUP_DESC(MAX96755_MFP2),
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GROUP_DESC(MAX96755_MFP3),
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GROUP_DESC_CONFIG(MAX96755_MFP4),
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GROUP_DESC_CONFIG(MAX96755_MFP5),
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GROUP_DESC(MAX96755_MFP6),
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GROUP_DESC_CONFIG(MAX96755_MFP7),
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GROUP_DESC_CONFIG(MAX96755_MFP8),
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GROUP_DESC_CONFIG(MAX96755_MFP9),
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GROUP_DESC_CONFIG(MAX96755_MFP10),
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GROUP_DESC_CONFIG(MAX96755_MFP11),
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GROUP_DESC_CONFIG(MAX96755_MFP12),
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GROUP_DESC_CONFIG(MAX96755_MFP13),
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GROUP_DESC_CONFIG(MAX96755_MFP14),
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GROUP_DESC_CONFIG(MAX96755_MFP15),
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GROUP_DESC_CONFIG(MAX96755_MFP16),
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GROUP_DESC_CONFIG(MAX96755_MFP17),
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GROUP_DESC_CONFIG(MAX96755_MFP18),
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GROUP_DESC(MAX96755_MFP19),
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GROUP_DESC(MAX96755_MFP20),
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GROUP_DESC(MAX96755_I2C),
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GROUP_DESC(MAX96755_UART),
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};
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static struct function_desc max96755_functions_desc[] = {
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FUNCTION_DESC_GPIO_INPUT(0),
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FUNCTION_DESC_GPIO_INPUT(1),
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FUNCTION_DESC_GPIO_INPUT(2),
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FUNCTION_DESC_GPIO_INPUT(3),
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FUNCTION_DESC_GPIO_INPUT(4),
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FUNCTION_DESC_GPIO_INPUT(5),
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FUNCTION_DESC_GPIO_INPUT(6),
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FUNCTION_DESC_GPIO_INPUT(7),
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FUNCTION_DESC_GPIO_INPUT(8),
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FUNCTION_DESC_GPIO_INPUT(9),
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FUNCTION_DESC_GPIO_INPUT(10),
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FUNCTION_DESC_GPIO_INPUT(11),
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FUNCTION_DESC_GPIO_INPUT(12),
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FUNCTION_DESC_GPIO_INPUT(13),
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FUNCTION_DESC_GPIO_INPUT(14),
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FUNCTION_DESC_GPIO_INPUT(15),
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FUNCTION_DESC_GPIO_INPUT(16),
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FUNCTION_DESC_GPIO_INPUT(17),
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FUNCTION_DESC_GPIO_INPUT(18),
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FUNCTION_DESC_GPIO_INPUT(19),
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FUNCTION_DESC_GPIO_INPUT(20),
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FUNCTION_DESC_GPIO_OUTPUT(0),
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FUNCTION_DESC_GPIO_OUTPUT(1),
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FUNCTION_DESC_GPIO_OUTPUT(2),
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FUNCTION_DESC_GPIO_OUTPUT(3),
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FUNCTION_DESC_GPIO_OUTPUT(4),
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FUNCTION_DESC_GPIO_OUTPUT(5),
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FUNCTION_DESC_GPIO_OUTPUT(6),
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FUNCTION_DESC_GPIO_OUTPUT(7),
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FUNCTION_DESC_GPIO_OUTPUT(8),
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FUNCTION_DESC_GPIO_OUTPUT(9),
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FUNCTION_DESC_GPIO_OUTPUT(10),
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FUNCTION_DESC_GPIO_OUTPUT(11),
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FUNCTION_DESC_GPIO_OUTPUT(12),
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FUNCTION_DESC_GPIO_OUTPUT(13),
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FUNCTION_DESC_GPIO_OUTPUT(14),
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FUNCTION_DESC_GPIO_OUTPUT(15),
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FUNCTION_DESC_GPIO_OUTPUT(16),
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FUNCTION_DESC_GPIO_OUTPUT(17),
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FUNCTION_DESC_GPIO_OUTPUT(18),
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FUNCTION_DESC_GPIO_OUTPUT(19),
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FUNCTION_DESC_GPIO_OUTPUT(20),
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FUNCTION_DESC(MAX96755_I2C),
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FUNCTION_DESC(MAX96755_UART),
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};
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static struct serdes_chip_pinctrl_info max96755_pinctrl_info = {
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.pins = max96755_pins_desc,
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.num_pins = ARRAY_SIZE(max96755_pins_desc),
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.groups = max96755_groups_desc,
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.num_groups = ARRAY_SIZE(max96755_groups_desc),
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.functions = max96755_functions_desc,
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.num_functions = ARRAY_SIZE(max96755_functions_desc),
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};
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static int max96755_bridge_init(struct serdes *serdes)
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{
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return 0;
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}
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static bool max96755_bridge_link_locked(struct serdes *serdes)
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{
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u32 val;
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if (serdes->lock_gpio)
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return gpiod_get_value_cansleep(serdes->lock_gpio);
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if (serdes_reg_read(serdes, 0x0013, &val))
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return false;
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if (!FIELD_GET(LOCKED, val))
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return false;
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return true;
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}
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static int max96755_bridge_attach(struct serdes *serdes)
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{
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if (max96755_bridge_link_locked(serdes))
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serdes->serdes_bridge->status = connector_status_connected;
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else
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serdes->serdes_bridge->status = connector_status_disconnected;
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return 0;
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}
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static enum drm_connector_status
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max96755_bridge_detect(struct serdes *serdes)
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{
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struct serdes_bridge *serdes_bridge = serdes->serdes_bridge;
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enum drm_connector_status status = connector_status_connected;
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|
if (!drm_kms_helper_is_poll_worker())
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return serdes_bridge->status;
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if (!max96755_bridge_link_locked(serdes)) {
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status = connector_status_disconnected;
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goto out;
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}
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if (extcon_get_state(serdes->extcon, EXTCON_JACK_VIDEO_OUT)) {
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if (atomic_cmpxchg(&serdes_bridge->triggered, 1, 0)) {
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status = connector_status_disconnected;
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goto out;
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}
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} else {
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atomic_set(&serdes_bridge->triggered, 0);
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}
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|
if (serdes_bridge->next_bridge && (serdes_bridge->next_bridge->ops & DRM_BRIDGE_OP_DETECT))
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return drm_bridge_detect(serdes_bridge->next_bridge);
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|
out:
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serdes_bridge->status = status;
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SERDES_DBG_MFD("%s: status=%d\n", __func__, status);
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return status;
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}
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static int max96755_bridge_enable(struct serdes *serdes)
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{
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int ret = 0;
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SERDES_DBG_CHIP("%s: serdes chip %s ret=%d\n", __func__, serdes->chip_data->name, ret);
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return ret;
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}
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static int max96755_bridge_disable(struct serdes *serdes)
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{
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int ret = 0;
|
|
return ret;
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}
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static struct serdes_chip_bridge_ops max96755_bridge_ops = {
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.init = max96755_bridge_init,
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.attach = max96755_bridge_attach,
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.detect = max96755_bridge_detect,
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.enable = max96755_bridge_enable,
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.disable = max96755_bridge_disable,
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};
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static int max96755_pinctrl_set_mux(struct serdes *serdes,
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unsigned int function, unsigned int group)
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{
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struct serdes_pinctrl *pinctrl = serdes->pinctrl;
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struct function_desc *func;
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struct group_desc *grp;
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int i;
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func = pinmux_generic_get_function(pinctrl->pctl, function);
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if (!func)
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return -EINVAL;
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grp = pinctrl_generic_get_group(pinctrl->pctl, group);
|
if (!grp)
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return -EINVAL;
|
|
SERDES_DBG_CHIP("%s: serdes chip %s func=%s data=%p group=%s data=%p, num_pin=%d\n",
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__func__, serdes->chip_data->name, func->name,
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func->data, grp->name, grp->data, grp->num_pins);
|
|
if (func->data) {
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struct serdes_function_data *fdata = func->data;
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for (i = 0; i < grp->num_pins; i++) {
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serdes_set_bits(serdes, GPIO_A_REG(grp->pins[i] - pinctrl->pin_base),
|
GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
|
FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
|
FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
|
FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en));
|
|
if (fdata->gpio_tx_en)
|
serdes_set_bits(serdes,
|
GPIO_B_REG(grp->pins[i] - pinctrl->pin_base),
|
GPIO_TX_ID,
|
FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
|
|
if (fdata->gpio_rx_en)
|
serdes_set_bits(serdes,
|
GPIO_C_REG(grp->pins[i] - pinctrl->pin_base),
|
GPIO_RX_ID,
|
FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
|
}
|
}
|
|
if (grp->data) {
|
struct serdes_group_data *gdata = grp->data;
|
|
for (i = 0; i < gdata->num_configs; i++) {
|
const struct config_desc *config = &gdata->configs[i];
|
|
serdes_set_bits(serdes, config->reg,
|
config->mask, config->val);
|
}
|
}
|
|
return 0;
|
}
|
|
static int max96755_pinctrl_config_get(struct serdes *serdes,
|
unsigned int pin, unsigned long *config)
|
{
|
enum pin_config_param param = pinconf_to_config_param(*config);
|
unsigned int gpio_a_reg, gpio_b_reg;
|
u16 arg = 0;
|
|
serdes_reg_read(serdes, GPIO_A_REG(pin), &gpio_a_reg);
|
serdes_reg_read(serdes, GPIO_B_REG(pin), &gpio_b_reg);
|
|
SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__,
|
serdes->chip_data->name, pin, param);
|
|
switch (param) {
|
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
if (FIELD_GET(OUT_TYPE, gpio_b_reg))
|
return -EINVAL;
|
break;
|
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
if (!FIELD_GET(OUT_TYPE, gpio_b_reg))
|
return -EINVAL;
|
break;
|
case PIN_CONFIG_BIAS_DISABLE:
|
if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0)
|
return -EINVAL;
|
break;
|
case PIN_CONFIG_BIAS_PULL_UP:
|
if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1)
|
return -EINVAL;
|
switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
|
case 0:
|
arg = 40000;
|
break;
|
case 1:
|
arg = 10000;
|
break;
|
}
|
break;
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2)
|
return -EINVAL;
|
switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
|
case 0:
|
arg = 40000;
|
break;
|
case 1:
|
arg = 10000;
|
break;
|
}
|
break;
|
case PIN_CONFIG_OUTPUT:
|
if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg))
|
return -EINVAL;
|
|
arg = FIELD_GET(GPIO_OUT, gpio_a_reg);
|
break;
|
default:
|
return -EOPNOTSUPP;
|
}
|
|
*config = pinconf_to_config_packed(param, arg);
|
|
return 0;
|
}
|
|
static int max96755_pinctrl_config_set(struct serdes *serdes,
|
unsigned int pin, unsigned long *configs,
|
unsigned int num_configs)
|
{
|
enum pin_config_param param;
|
u32 arg;
|
u8 res_cfg;
|
int i;
|
|
for (i = 0; i < num_configs; i++) {
|
param = pinconf_to_config_param(configs[i]);
|
arg = pinconf_to_config_argument(configs[i]);
|
|
SERDES_DBG_CHIP("%s: serdes chip %s pin=%d param=%d\n", __func__,
|
serdes->chip_data->name, pin, param);
|
|
switch (param) {
|
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
serdes_set_bits(serdes, GPIO_B_REG(pin),
|
OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
|
break;
|
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
serdes_set_bits(serdes, GPIO_B_REG(pin),
|
OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
|
break;
|
case PIN_CONFIG_BIAS_DISABLE:
|
serdes_set_bits(serdes, GPIO_C_REG(pin),
|
PULL_UPDN_SEL,
|
FIELD_PREP(PULL_UPDN_SEL, 0));
|
break;
|
case PIN_CONFIG_BIAS_PULL_UP:
|
switch (arg) {
|
case 40000:
|
res_cfg = 0;
|
break;
|
case 1000000:
|
res_cfg = 1;
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
serdes_set_bits(serdes, GPIO_A_REG(pin),
|
RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
|
serdes_set_bits(serdes, GPIO_C_REG(pin),
|
PULL_UPDN_SEL,
|
FIELD_PREP(PULL_UPDN_SEL, 1));
|
break;
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
switch (arg) {
|
case 40000:
|
res_cfg = 0;
|
break;
|
case 1000000:
|
res_cfg = 1;
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
serdes_set_bits(serdes, GPIO_A_REG(pin),
|
RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
|
serdes_set_bits(serdes, GPIO_C_REG(pin),
|
PULL_UPDN_SEL,
|
FIELD_PREP(PULL_UPDN_SEL, 2));
|
break;
|
case PIN_CONFIG_OUTPUT:
|
serdes_set_bits(serdes, GPIO_A_REG(pin),
|
GPIO_OUT_DIS | GPIO_OUT,
|
FIELD_PREP(GPIO_OUT_DIS, 0) |
|
FIELD_PREP(GPIO_OUT, arg));
|
break;
|
default:
|
return -EOPNOTSUPP;
|
}
|
}
|
|
return 0;
|
}
|
|
static struct serdes_chip_pinctrl_ops max96755_pinctrl_ops = {
|
.pin_config_get = max96755_pinctrl_config_get,
|
.pin_config_set = max96755_pinctrl_config_set,
|
.set_mux = max96755_pinctrl_set_mux,
|
};
|
|
static int max96755_gpio_direction_input(struct serdes *serdes, int gpio)
|
{
|
return 0;
|
}
|
|
static int max96755_gpio_direction_output(struct serdes *serdes, int gpio, int value)
|
{
|
return 0;
|
}
|
|
static int max96755_gpio_get_level(struct serdes *serdes, int gpio)
|
{
|
return 0;
|
}
|
|
static int max96755_gpio_set_level(struct serdes *serdes, int gpio, int value)
|
{
|
return 0;
|
}
|
|
static int max96755_gpio_set_config(struct serdes *serdes, int gpio, unsigned long config)
|
{
|
return 0;
|
}
|
|
static int max96755_gpio_to_irq(struct serdes *serdes, int gpio)
|
{
|
return 0;
|
}
|
|
static struct serdes_chip_gpio_ops max96755_gpio_ops = {
|
.direction_input = max96755_gpio_direction_input,
|
.direction_output = max96755_gpio_direction_output,
|
.get_level = max96755_gpio_get_level,
|
.set_level = max96755_gpio_set_level,
|
.set_config = max96755_gpio_set_config,
|
.to_irq = max96755_gpio_to_irq,
|
};
|
|
static int max96755_pm_suspend(struct serdes *serdes)
|
{
|
return 0;
|
}
|
|
static int max96755_pm_resume(struct serdes *serdes)
|
{
|
return 0;
|
}
|
|
static struct serdes_chip_pm_ops max96755_pm_ops = {
|
.suspend = max96755_pm_suspend,
|
.resume = max96755_pm_resume,
|
};
|
|
static int max96755_irq_lock_handle(struct serdes *serdes)
|
{
|
return IRQ_HANDLED;
|
}
|
|
static int max96755_irq_err_handle(struct serdes *serdes)
|
{
|
return IRQ_HANDLED;
|
}
|
|
static struct serdes_chip_irq_ops max96755_irq_ops = {
|
.lock_handle = max96755_irq_lock_handle,
|
.err_handle = max96755_irq_err_handle,
|
};
|
|
struct serdes_chip_data serdes_max96755_data = {
|
.name = "max96755",
|
.serdes_type = TYPE_SER,
|
.serdes_id = MAXIM_ID_MAX96755,
|
.connector_type = DRM_MODE_CONNECTOR_LVDS,
|
.regmap_config = &max96755_regmap_config,
|
.pinctrl_info = &max96755_pinctrl_info,
|
.bridge_ops = &max96755_bridge_ops,
|
.pinctrl_ops = &max96755_pinctrl_ops,
|
.gpio_ops = &max96755_gpio_ops,
|
.pm_ops = &max96755_pm_ops,
|
.irq_ops = &max96755_irq_ops,
|
};
|
EXPORT_SYMBOL_GPL(serdes_max96755_data);
|
|
MODULE_LICENSE("GPL");
|
