/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd. */
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#ifndef _RKISP_EXTERNAL_H
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#define _RKISP_EXTERNAL_H
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#define RKISP_VICAP_CMD_MODE \
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_IOWR('V', BASE_VIDIOC_PRIVATE + 0, struct rkisp_vicap_mode)
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#define RKISP_VICAP_CMD_INIT_BUF \
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_IOW('V', BASE_VIDIOC_PRIVATE + 1, int)
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#define RKISP_VICAP_CMD_RX_BUFFER_FREE \
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_IOW('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_rx_buf)
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#define RKISP_VICAP_BUF_CNT 3
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#define RKISP_VICAP_BUF_CNT_MAX 8
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#define RKISP_RX_BUF_POOL_MAX (RKISP_VICAP_BUF_CNT_MAX * 3)
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struct rkisp_vicap_input {
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u8 merge_num;
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u8 index;
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};
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enum rkisp_vicap_link {
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RKISP_VICAP_ONLINE,
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RKISP_VICAP_RDBK_AIQ,
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RKISP_VICAP_RDBK_AUTO,
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};
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struct rkisp_vicap_mode {
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char *name;
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enum rkisp_vicap_link rdbk_mode;
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struct rkisp_vicap_input input;
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};
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enum rx_buf_type {
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BUF_SHORT,
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BUF_MIDDLE,
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BUF_LONG,
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};
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struct rkisp_rx_buf {
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struct list_head list;
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struct dma_buf *dbuf;
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dma_addr_t dma;
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u64 timestamp;
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u32 sequence;
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u32 type;
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u32 runtime_us;
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bool is_init;
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bool is_first;
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bool is_resmem;
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bool is_switch;
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bool is_uncompact;
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};
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#endif
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