/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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*
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* Author: Dingxian Wen <shawn.wen@rock-chips.com>
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*/
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#ifndef __RK_HDMIRX_H__
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#define __RK_HDMIRX_H__
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#include <linux/bitops.h>
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#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
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#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16))
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// -------------------- SYS_GRF ---------------------------------
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#define SYS_GRF_SOC_CON1 0x0304
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#define HDMIRXPHY_SRAM_EXT_LD_DONE BIT(1)
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#define HDMIRXPHY_SRAM_BYPASS BIT(0)
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#define SYS_GRF_SOC_STATUS1 0x0384
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#define HDMIRXPHY_SRAM_INIT_DONE BIT(10)
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#define SYS_GRF_CHIP_ID 0x0600
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// -------------------- VO1_GRF ---------------------------------
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#define VO1_GRF_VO1_CON1 0x0004
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#define HDCP1_P0_GPIO_IN_SEL BIT(8)
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#define VO1_GRF_VO1_CON2 0x0008
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#define HDCP1_GATING_EN BIT(10)
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#define HDMIRX_SDAIN_MSK BIT(2)
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#define HDMIRX_SCLIN_MSK BIT(1)
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#define HDCP2_SWITCH_LCK BIT(0)
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#define HDCP2_ESM_P0_GPIO_IN 0x0300
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// -------------------- HDMIRX PHY -------------------------------
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#define SUP_DIG_ANA_CREGS_SUP_ANA_NC 0x004f
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#define LANE0_DIG_ASIC_RX_OVRD_OUT_0 0x100f
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#define LANE1_DIG_ASIC_RX_OVRD_OUT_0 0x110f
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#define LANE2_DIG_ASIC_RX_OVRD_OUT_0 0x120f
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#define LANE3_DIG_ASIC_RX_OVRD_OUT_0 0x130f
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#define ASIC_ACK_OVRD_EN BIT(1)
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#define ASIC_ACK BIT(0)
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#define LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x104a
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#define LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x114a
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#define LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x124a
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#define LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2 0x134a
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#define FREQ_TUNE_START_VAL_MASK GENMASK(9, 0)
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#define FREQ_TUNE_START_VAL(x) UPDATE(x, 9, 0)
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#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_FSM_CONFIG 0x20c4
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#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_ADAPT_REF_FOM 0x20c7
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#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_3_REG 0x20e9
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#define CDR_SETTING_BOUNDARY_3_DEFAULT 0x52da
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#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_4_REG 0x20ea
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#define CDR_SETTING_BOUNDARY_4_DEFAULT 0x43cd
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#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_5_REG 0x20eb
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#define CDR_SETTING_BOUNDARY_5_DEFAULT 0x35b3
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#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_6_REG 0x20fb
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#define CDR_SETTING_BOUNDARY_6_DEFAULT 0x2799
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#define HDMIPCS_DIG_CTRL_PATH_MAIN_FSM_RATE_CALC_HDMI14_CDR_SETTING_7_REG 0x20fc
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#define CDR_SETTING_BOUNDARY_7_DEFAULT 0x1b65
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#define RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT 0x300e
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#define RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT 0x310e
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#define RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT 0x320e
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#define RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT 0x330e
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#define PCS_ACK_WRITE_SELECT BIT(14)
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#define PCS_EN_CTL BIT(1)
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#define PCS_ACK BIT(0)
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#define RAWLANE0_DIG_AON_FAST_FLAGS 0x305c
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#define RAWLANE1_DIG_AON_FAST_FLAGS 0x315c
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#define RAWLANE2_DIG_AON_FAST_FLAGS 0x325c
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#define RAWLANE3_DIG_AON_FAST_FLAGS 0x335c
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// -------------------- HDMIRX Ctrler -------------------------------
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#define GLOBAL_SWRESET_REQUEST 0x0020
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#define DATAPATH_SWRESETREQ BIT(12)
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#define AUDIO_SWRESETREQ BIT(9)
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#define GLOBAL_SWENABLE 0x0024
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#define PHYCTRL_ENABLE BIT(21)
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#define CEC_ENABLE BIT(16)
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#define TMDS_ENABLE BIT(13)
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#define DATAPATH_ENABLE BIT(12)
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#define PKTFIFO_ENABLE BIT(11)
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#define HDCP_ENABLE BIT(10)
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#define AUDIO_ENABLE BIT(9)
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#define AVPUNIT_ENABLE BIT(8)
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#define MAIN_ENABLE BIT(0)
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#define GLOBAL_TIMER_REF_BASE 0x0028
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#define CORE_CONFIG 0x0050
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#define CMU_CONFIG0 0x0060
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#define TMDSQPCLK_STABLE_FREQ_MARGIN_MASK GENMASK(30, 16)
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#define TMDSQPCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 30, 16)
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#define AUDCLK_STABLE_FREQ_MARGIN_MASK GENMASK(11, 9)
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#define AUDCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 11, 9)
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#define CMU_STATUS 0x007c
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#define TMDSQPCLK_LOCKED_ST BIT(4)
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#define CMU_TMDSQPCLK_FREQ 0x0084
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#define PHY_CONFIG 0x00c0
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#define LDO_AFE_PROG_MASK GENMASK(24, 23)
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#define LDO_AFE_PROG(x) UPDATE(x, 24, 23)
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#define LDO_PWRDN BIT(21)
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#define TMDS_CLOCK_RATIO BIT(16)
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#define RXDATA_WIDTH BIT(15)
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#define REFFREQ_SEL_MASK GENMASK(11, 9)
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#define REFFREQ_SEL(x) UPDATE(x, 11, 9)
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#define HDMI_DISABLE BIT(8)
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#define PHY_PDDQ BIT(1)
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#define PHY_RESET BIT(0)
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#define PHY_STATUS 0x00c8
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#define HDMI_DISABLE_ACK BIT(1)
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#define PDDQ_ACK BIT(0)
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#define PHYCREG_CONFIG0 0x00e0
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#define PHYCREG_CR_PARA_SELECTION_MODE_MASK GENMASK(1, 0)
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#define PHYCREG_CR_PARA_SELECTION_MODE(x) UPDATE(x, 1, 0)
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#define PHYCREG_CONFIG1 0x00e4
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#define PHYCREG_CONFIG2 0x00e8
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#define PHYCREG_CONFIG3 0x00ec
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#define PHYCREG_CONTROL 0x00f0
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#define PHYCREG_CR_PARA_WRITE_P BIT(1)
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#define PHYCREG_CR_PARA_READ_P BIT(0)
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#define PHYCREG_STATUS 0x00f4
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#define MAINUNIT_STATUS 0x0150
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#define TMDSVALID_STABLE_ST BIT(1)
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#define DESCRAND_EN_CONTROL 0x0210
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#define SCRAMB_EN_SEL_QST_MASK GENMASK(1, 0)
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#define SCRAMB_EN_SEL_QST(x) UPDATE(x, 1, 0)
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#define DESCRAND_SYNC_CONTROL 0x0214
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#define RECOVER_UNSYNC_STREAM_QST BIT(0)
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#define DESCRAND_SYNC_SEQ_CONFIG 0x022c
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#define DESCRAND_SYNC_SEQ_ERR_CNT_EN BIT(0)
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#define DESCRAND_SYNC_SEQ_STATUS 0x0234
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#define DEFRAMER_CONFIG0 0x0270
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#define VS_CNT_THR_QST_MASK GENMASK(27, 20)
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#define VS_CNT_THR_QST(x) UPDATE(x, 27, 20)
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#define HS_POL_QST_MASK GENMASK(19, 18)
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#define HS_POL_QST(x) UPDATE(x, 19, 18)
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#define VS_POL_QST_MASK GENMASK(17, 16)
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#define VS_POL_QST(x) UPDATE(x, 17, 16)
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#define VS_REMAPFILTER_EN_QST BIT(8)
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#define HS_FILTER_ORDER_QST_MASK GENMASK(3, 2)
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#define HS_FILTER_ORDER_QST(x) UPDATE(x, 3, 2)
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#define VS_FILTER_ORDER_QST_MASK GENMASK(1, 0)
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#define VS_FILTER_ORDER_QST(x) UPDATE(x, 1, 0)
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#define DEFRAMER_VSYNC_CNT_CLEAR 0x0278
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#define VSYNC_CNT_CLR_P BIT(0)
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#define DEFRAMER_STATUS 0x027c
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#define OPMODE_STS_MASK GENMASK(6, 4)
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#define I2C_SLAVE_CONFIG1 0x0164
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#define I2C_SDA_OUT_HOLD_VALUE_QST_MASK GENMASK(15, 8)
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#define I2C_SDA_OUT_HOLD_VALUE_QST(x) UPDATE(x, 15, 8)
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#define I2C_SDA_IN_HOLD_VALUE_QST_MASK GENMASK(7, 0)
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#define I2C_SDA_IN_HOLD_VALUE_QST(x) UPDATE(x, 7, 0)
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#define OPMODE_STS_MASK GENMASK(6, 4)
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#define HDCP14_CONFIG 0x0290
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#define REPEATER_QST BIT(28)
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#define FASTREAUTH_QST BIT(27)
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#define FEATURES_1DOT1_QST BIT(26)
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#define FASTI2C_QST BIT(25)
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#define EESS_CTL_THR_QST_MASK GENMASK(19, 16)
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#define EESS_CTL_THR_QST(x) UPDATE(x, 19, 16)
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#define OESS_CTL3_THR_QST_MASK GENMASK(11, 8)
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#define OESS_CTL3_THR_QST(x) UPDATE(x, 11, 8)
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#define EESS_OESS_SEL_QST_MASK GENMASK(5, 4)
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#define EESS_OESS_SEL_QST(x) UPDATE(x, 5, 4)
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#define KEY_DECRYPT_EN_QST BIT(0)
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#define HDCP14_KEY_SEED 0x02a0
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#define KEY_DECRYPT_SEED_QST_MASK GENMASK(15, 0)
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#define KEY_DECRYPT_SEED_QST(x) UPDATE(x, 15, 0)
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#define HDCP14_STATUS 0x2b8
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#define HDCP2_CONFIG 0x02f0
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#define HDCP2_CONNECTED BIT(12)
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#define HDCP2_SWITCH_OVR_VALUE BIT(2)
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#define HDCP2_SWITCH_OVR_EN BIT(1)
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#define HDCP2_STATUS 0x02f4
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#define HDCP2_ESM_P0_GPIO_OUT 0x0304
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#define VIDEO_CONFIG2 0x042c
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#define VPROC_VSYNC_POL_OVR_VALUE BIT(19)
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#define VPROC_VSYNC_POL_OVR_EN BIT(18)
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#define VPROC_HSYNC_POL_OVR_VALUE BIT(17)
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#define VPROC_HSYNC_POL_OVR_EN BIT(16)
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#define VPROC_FMT_OVR_VALUE_MASK GENMASK(6, 4)
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#define VPROC_FMT_OVR_VALUE(x) UPDATE(x, 6, 4)
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#define VPROC_FMT_OVR_EN BIT(0)
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#define VIDEO_MUTE_VALUE_H 0x0430
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#define VIDEO_MUTE_VALUE_L 0x0434
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#define AUDIO_FIFO_CONFIG 0x0460
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#define AFIFO_FILL_RESTART BIT(0)
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#define AUDIO_FIFO_CONTROL 0x0464
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#define AFIFO_INIT_P BIT(0)
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#define AUDIO_FIFO_THR_PASS 0x0468
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#define AUDIO_FIFO_THR 0x046c
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#define AFIFO_THR_LOW_QST_MASK GENMASK(25, 16)
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#define AFIFO_THR_LOW_QST(x) UPDATE(x, 25, 16)
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#define AFIFO_THR_HIGH_QST_MASK GENMASK(9, 0)
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#define AFIFO_THR_HIGH_QST(x) UPDATE(x, 9, 0)
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#define AUDIO_FIFO_MUTE_THR 0x0470
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#define AFIFO_THR_MUTE_LOW_QST_MASK GENMASK(25, 16)
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#define AFIFO_THR_MUTE_LOW_QST(x) UPDATE(x, 25, 16)
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#define AFIFO_THR_MUTE_HIGH_QST_MASK GENMASK(9, 0)
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#define AFIFO_THR_MUTE_HIGH_QST(x) UPDATE(x, 9, 0)
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#define AUDIO_FIFO_STATUS2 0x0478
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#define AFIFO_UNDERFLOW_ST BIT(25)
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#define AFIFO_OVERFLOW_ST BIT(24)
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#define AUDIO_PROC_CONFIG0 0x0480
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#define SPEAKER_ALLOC_OVR_EN BIT(16)
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#define AUD_MUTE_OVR_VALUE BIT(13)
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#define AUD_MUTE_OVR_EN BIT(12)
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#define I2S_BPCUV_EN BIT(4)
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#define SPDIF_EN BIT(2)
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#define I2S_EN BIT(1)
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#define AUDIO_PROC_CONFIG1 0x0484
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#define AUDIO_PROC_CONFIG2 0x0488
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#define AFIFO_THR_PASS_DEMUTEMASK_N BIT(24)
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#define AVMUTE_DEMUTEMASK_N BIT(16)
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#define AFIFO_THR_MUTE_LOW_MUTEMASK_N BIT(9)
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#define AFIFO_THR_MUTE_HIGH_MUTEMASK_N BIT(8)
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#define AUD_FMT_CHG_MUTEMASK_N BIT(1)
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#define AVMUTE_MUTEMASK_N BIT(0)
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#define AUDIO_PROC_CONFIG3 0x048c
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#define AUDIO_PROC_STATUS1 0x0490
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#define AUD_SAMPLE_PRESENT GENMASK(20, 17)
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#define AUD_SAMPLE_FLAT GENMASK(16, 13)
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#define SCDC_CONFIG 0x0580
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#define HPDLOW BIT(1)
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#define POWERPROVIDED BIT(0)
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#define SCDC_REGBANK_STATUS1 0x058c
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#define SCDC_TMDSBITCLKRATIO BIT(1)
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#define SCDC_REGBANK_STATUS3 0x0594
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#define SCDC_REGBANK_CONFIG0 0x05c0
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#define SCDC_SINKVERSION_QST_MASK GENMASK(7, 0)
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#define SCDC_SINKVERSION_QST(x) UPDATE(x, 7, 0)
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#define AUDIO_GEN_CONFIG0 0x0740
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#define AGEN_LAYOUT BIT(4)
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#define AGEN_SPEAKER_ALLOC GENMASK(15, 8)
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#define CED_CONFIG 0x0760
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#define CED_VIDDATACHECKEN_QST BIT(27)
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#define CED_DATAISCHECKEN_QST BIT(26)
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#define CED_GBCHECKEN_QST BIT(25)
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#define CED_CTRLCHECKEN_QST BIT(24)
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#define CED_CHLOCKMAXER_QST_MASK GENMASK(14, 0)
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#define CED_CHLOCKMAXER_QST(x) UPDATE(x, 14, 0)
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#define CED_DYN_CONFIG 0x0768
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#define CED_DYN_CONTROL 0x076c
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#define PKTEX_BCH_ERRFILT_CONFIG 0x07c4
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#define PKTEX_CHKSUM_ERRFILT_CONFIG 0x07c8
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#define PKTDEC_ACR_PH2_1 0x1100
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#define PKTDEC_ACR_PB3_0 0x1104
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#define PKTDEC_ACR_PB7_4 0x1108
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#define PKTDEC_AVIIF_PH2_1 0x1200
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#define PKTDEC_AVIIF_PB3_0 0x1204
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#define RGB_QUANTIZATION_RANGE GENMASK(27, 26)
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#define EXTEND_COLORIMETRY GENMASK(30, 28)
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#define PKTDEC_AVIIF_PB7_4 0x1208
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#define VIC_VAL_MASK GENMASK(6, 0)
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#define PKTDEC_AVIIF_PB11_8 0x120c
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#define PKTDEC_AVIIF_PB15_12 0x1210
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#define PKTDEC_AVIIF_PB19_16 0x1214
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#define PKTDEC_AVIIF_PB23_20 0x1218
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#define PKTDEC_AVIIF_PB27_24 0x121c
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#define PKTDEC_AUDIF_PH2_1 0x1240
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#define PKTDEC_AUDIF_PB3_0 0x1244
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#define PKTDEC_AUDIF_PB7_4 0x1248
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#define PKTDEC_AUDIF_PB11_8 0x124c
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#define PKTDEC_AUDIF_PB15_12 0x1250
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#define PKTDEC_AUDIF_PB19_16 0x1254
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#define PKTDEC_AUDIF_PB23_20 0x1258
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#define PKTDEC_AUDIF_PB27_24 0x125c
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#define PKTFIFO_CONFIG 0x1500
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#define PKTFIFO_STORE_FILT_CONFIG 0x1504
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#define PKTFIFO_THR_CONFIG0 0x1508
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#define PKTFIFO_THR_CONFIG1 0x150c
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#define PKTFIFO_CONTROL 0x1510
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#define VMON_CONTROL 0x1560
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#define VMON_SOURCE_SEL_MASK GENMASK(30, 28)
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#define VMON_SOURCE_SEL_DEFRAMER(x) UPDATE(x, 30, 28)
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#define VMON_IRQ_THR_MASK BIT(24)
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#define VMON_CONTROL2 0x1564
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#define VMON_IRQ_VERTICAL_MASK GENMASK(12, 8)
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#define VMON_IRQ_VERTICAL_SEL(x) UPDATE(x, 12, 8)
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#define VMON_IRQ_HORIZONAL_MASK GENMASK(4, 0)
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#define VMON_IRQ_HORIZONAL_SEL(x) UPDATE(x, 4, 0)
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#define VMON_STATUS1 0x1580
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#define VMON_STATUS2 0x1584
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#define VMON_STATUS3 0x1588
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#define VMON_STATUS4 0x158c
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#define VMON_STATUS5 0x1590
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#define VMON_STATUS6 0x1594
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#define VMON_STATUS7 0x1598
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#define VMON_ILACE_DETECT BIT(4)
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#define CEC_TX_CONTROL 0x2000
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#define CEC_STATUS 0x2004
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#define CEC_CONFIG 0x2008
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#define RX_AUTO_DRIVE_ACKNOWLEDGE BIT(9)
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#define CEC_ADDR 0x200c
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#define CEC_TX_COUNT 0x2020
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#define CEC_TX_DATA3_0 0x2024
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#define CEC_RX_COUNT_STATUS 0x2040
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#define CEC_RX_DATA3_0 0x2044
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#define CEC_LOCK_CONTROL 0x2054
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#define CEC_RXQUAL_BITTIME_CONFIG 0x2060
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#define CEC_RX_BITTIME_CONFIG 0x2064
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#define CEC_TX_BITTIME_CONFIG 0x2068
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#define DMA_CONFIG1 0x4400
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#define UV_WID_MASK GENMASK(31, 28)
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#define UV_WID(x) UPDATE(x, 31, 28)
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#define Y_WID_MASK GENMASK(27, 24)
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#define Y_WID(x) UPDATE(x, 27, 24)
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#define DDR_STORE_FORMAT_MASK GENMASK(15, 12)
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#define DDR_STORE_FORMAT(x) UPDATE(x, 15, 12)
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#define ABANDON_EN BIT(0)
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#define DMA_CONFIG2 0x4404
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#define DMA_CONFIG3 0x4408
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#define DMA_CONFIG4 0x440c // dma irq en
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#define DMA_CONFIG5 0x4410 // dma irq clear status
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#define LINE_FLAG_INT_EN BIT(8)
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#define HDMIRX_DMA_IDLE_INT BIT(7)
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#define HDMIRX_LOCK_DISABLE_INT BIT(6)
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#define LAST_FRAME_AXI_UNFINISH_INT_EN BIT(5)
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#define FIFO_OVERFLOW_INT_EN BIT(2)
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#define FIFO_UNDERFLOW_INT_EN BIT(1)
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#define HDMIRX_AXI_ERROR_INT_EN BIT(0)
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#define DMA_CONFIG6 0x4414
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#define RB_SWAP_EN BIT(9)
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#define HSYNC_TOGGLE_EN BIT(5)
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#define VSYNC_TOGGLE_EN BIT(4)
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#define HDMIRX_DMA_EN BIT(1)
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#define DMA_CONFIG7 0x4418
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#define LINE_FLAG_NUM_MASK GENMASK(31, 16)
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#define LINE_FLAG_NUM(x) UPDATE(x, 31, 16)
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#define LOCK_FRAME_NUM_MASK GENMASK(11, 0)
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#define LOCK_FRAME_NUM(x) UPDATE(x, 11, 0)
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#define DMA_CONFIG8 0x441c
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#define REG_MIRROR_EN BIT(0)
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#define DMA_CONFIG9 0x4420
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#define DMA_CONFIG10 0x4424
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#define DMA_CONFIG11 0x4428
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#define EDID_READ_EN_MASK BIT(8)
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#define EDID_READ_EN(x) UPDATE(x, 8, 8)
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#define EDID_WRITE_EN_MASK BIT(7)
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#define EDID_WRITE_EN(x) UPDATE(x, 7, 7)
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#define EDID_SLAVE_ADDR_MASK GENMASK(6, 0)
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#define EDID_SLAVE_ADDR(x) UPDATE(x, 6, 0)
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#define DMA_STATUS1 0x4430 // dma irq status
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#define DMA_STATUS2 0x4434
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#define DMA_STATUS3 0x4438
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#define DMA_STATUS4 0x443c
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#define DMA_STATUS5 0x4440
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#define DMA_STATUS6 0x4444
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#define DMA_STATUS7 0x4448
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#define DMA_STATUS8 0x444c
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#define DMA_STATUS9 0x4450
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#define DMA_STATUS10 0x4454
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#define HDMIRX_LOCK BIT(3)
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#define DMA_STATUS11 0x4458
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#define HDMIRX_TYPE_MASK GENMASK(8, 7)
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#define HDMIRX_COLOR_DEPTH_MASK GENMASK(6, 3)
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#define HDMIRX_FORMAT_MASK GENMASK(2, 0)
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#define DMA_STATUS12 0x445c
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#define DMA_STATUS13 0x4460
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#define DMA_STATUS14 0x4464
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#define MAINUNIT_INTVEC_INDEX 0x5000
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#define MAINUNIT_0_INT_STATUS 0x5010
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#define CECRX_NOTIFY_ERR BIT(12)
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#define CECRX_EOM BIT(11)
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#define CECTX_DRIVE_ERR BIT(10)
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#define CECRX_BUSY BIT(9)
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#define CECTX_BUSY BIT(8)
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#define CECTX_FRAME_DISCARDED BIT(5)
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#define CECTX_NRETRANSMIT_FAIL BIT(4)
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#define CECTX_LINE_ERR BIT(3)
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#define CECTX_ARBLOST BIT(2)
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#define CECTX_NACK BIT(1)
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#define CECTX_DONE BIT(0)
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#define MAINUNIT_0_INT_MASK_N 0x5014
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#define MAINUNIT_0_INT_CLEAR 0x5018
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#define MAINUNIT_0_INT_FORCE 0x501c
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#define TIMER_BASE_LOCKED_IRQ BIT(26)
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#define TMDSQPCLK_OFF_CHG BIT(5)
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#define TMDSQPCLK_LOCKED_CHG BIT(4)
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#define MAINUNIT_1_INT_STATUS 0x5020
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#define MAINUNIT_1_INT_MASK_N 0x5024
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#define MAINUNIT_1_INT_CLEAR 0x5028
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#define MAINUNIT_1_INT_FORCE 0x502c
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#define MAINUNIT_2_INT_STATUS 0x5030
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#define MAINUNIT_2_INT_MASK_N 0x5034
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#define MAINUNIT_2_INT_CLEAR 0x5038
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#define MAINUNIT_2_INT_FORCE 0x503c
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#define PHYCREG_CR_READ_DONE BIT(11)
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#define PHYCREG_CR_WRITE_DONE BIT(10)
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#define TMDSVALID_STABLE_CHG BIT(1)
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#define AVPUNIT_0_INT_STATUS 0x5040
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#define AVPUNIT_0_INT_MASK_N 0x5044
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#define AVPUNIT_0_INT_CLEAR 0x5048
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#define AVPUNIT_0_INT_FORCE 0x504c
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#define CED_DYN_CNT_CH2_IRQ BIT(22)
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#define CED_DYN_CNT_CH1_IRQ BIT(21)
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#define CED_DYN_CNT_CH0_IRQ BIT(20)
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#define AVPUNIT_1_INT_STATUS 0x5050
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#define VMON_VMEAS_IRQ BIT(31)
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#define VMON_HMEAS_IRQ BIT(30)
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#define DEFRAMER_VSYNC_THR_REACHED_IRQ BIT(1)
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#define AVPUNIT_1_INT_MASK_N 0x5054
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#define DEFRAMER_VSYNC_THR_REACHED_MASK_N BIT(1)
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#define DEFRAMER_VSYNC_MASK_N BIT(0)
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#define AVPUNIT_1_INT_CLEAR 0x5058
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#define DEFRAMER_VSYNC_THR_REACHED_CLEAR BIT(1)
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#define AVPUNIT_1_INT_FORCE 0x505C
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#define PKT_0_INT_STATUS 0x5080
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#define PKTDEC_AUDIF_CHG_IRQ BIT(13)
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#define PKTDEC_AVIIF_CHG_IRQ BIT(11)
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#define PKTDEV_VSIF_CHG_IRQ BIT(10)
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#define PKTDEC_ACR_CHG_IRQ BIT(3)
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#define PKT_0_INT_MASK_N 0x5084
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#define PKTDEC_AVIIF_CHG_MASK_N BIT(11)
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#define PKTDEV_VSIF_CHG_MASK_N BIT(10)
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#define PKTDEC_ACR_CHG_MASK_N BIT(3)
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#define PKT_0_INT_CLEAR 0x5088
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#define PKT_0_INT_FORCE 0x508c
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#define PKT_1_INT_STATUS 0x5090
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#define PKT_1_INT_MASK_N 0x5094
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#define PKT_1_INT_CLEAR 0x5098
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#define PKT_2_INT_STATUS 0x50a0
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#define PKTDEC_AUDIF_RCV_IRQ BIT(13)
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#define PKTDEC_ACR_RCV_IRQ BIT(3)
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#define PKT_2_INT_MASK_N 0x50a4
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#define PKTDEC_AUDIF_RCV_MASK_N BIT(13)
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#define PKTDEC_AVIIF_RCV_IRQ BIT(11)
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#define PKTDEC_ACR_RCV_MASK_N BIT(3)
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#define PKT_2_INT_CLEAR 0x50a8
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#define PKTDEC_AUDIF_RCV_CLEAR BIT(13)
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#define PKTDEC_AVIIF_RCV_CLEAR BIT(11)
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#define PKTDEC_ACR_RCV_CLEAR BIT(3)
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#define SCDC_INT_STATUS 0x50c0
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#define SCDC_INT_MASK_N 0x50c4
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#define SCDC_INT_CLEAR 0x50c8
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#define SCDCTMDSCCFG_CHG BIT(2)
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#define HDCP_INT_STATUS 0x50d0
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#define HDCP_INT_MASK_N 0x50d4
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#define HDCP_INT_CLEAR 0x50d8
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#define HDCP_1_INT_STATUS 0x50e0
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#define HDCP_1_INT_MASK_N 0x50e4
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#define HDCP_1_INT_CLEAR 0x50e8
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#define CEC_INT_STATUS 0x5100
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#define CEC_INT_MASK_N 0x5104
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#define CEC_INT_CLEAR 0x5108
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#endif
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