/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
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#ifndef _RKCIF_MIPI_CSI2_H_
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#define _RKCIF_MIPI_CSI2_H_
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#include <linux/notifier.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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#include <media/v4l2-event.h>
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#include <linux/rkcif-config.h>
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#define CSI2_ERR_FSFE_MASK (0xff << 8)
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#define CSI2_ERR_COUNT_ALL_MASK (0xff)
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#define RKCIF_V4L2_EVENT_ELEMS 4
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/*
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* there must be 5 pads: 1 input pad from sensor, and
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* the 4 virtual channel output pads
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*/
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#define CSI2_SINK_PAD 0
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#define CSI2_NUM_SINK_PADS 4
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#define CSI2_NUM_SRC_PADS 11
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#define CSI2_NUM_PADS 5
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#define CSI2_NUM_PADS_MAX 12
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#define CSI2_NUM_PADS_SINGLE_LINK 2
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#define MAX_CSI2_SENSORS 2
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#define RKCIF_DEFAULT_WIDTH 640
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#define RKCIF_DEFAULT_HEIGHT 480
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#define CSI_ERRSTR_LEN (256)
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#define CSI_VCINFO_LEN (12)
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/*
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* The default maximum bit-rate per lane in Mbps, if the
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* source subdev does not provide V4L2_CID_LINK_FREQ.
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*/
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#define CSI2_DEFAULT_MAX_MBPS 849
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#define IMX_MEDIA_GRP_ID_CSI2 BIT(8)
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#define CSIHOST_MAX_ERRINT_COUNT 10
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#define DEVICE_NAME "rockchip-mipi-csi2"
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#define DEVICE_NAME_HW "rockchip-mipi-csi2-hw"
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/* CSI Host Registers Define */
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#define CSIHOST_N_LANES 0x04
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#define CSIHOST_DPHY_SHUTDOWNZ 0x08
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#define CSIHOST_PHY_RSTZ 0x0c
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#define CSIHOST_RESETN 0x10
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#define CSIHOST_PHY_STATE 0x14
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#define CSIHOST_ERR1 0x20
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#define CSIHOST_ERR2 0x24
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#define CSIHOST_MSK1 0x28
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#define CSIHOST_MSK2 0x2c
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#define CSIHOST_CONTROL 0x40
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#define CSIHOST_ERR1_PHYERR_SPTSYNCHS 0x0000000f
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#define CSIHOST_ERR1_ERR_BNDRY_MATCH 0x000000f0
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#define CSIHOST_ERR1_ERR_SEQ 0x00000f00
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#define CSIHOST_ERR1_ERR_FRM_DATA 0x0000f000
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#define CSIHOST_ERR1_ERR_CRC 0x0f000000
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#define CSIHOST_ERR1_ERR_ECC2 0x10000000
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#define CSIHOST_ERR1_ERR_CTRL 0x000f0000
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#define CSIHOST_ERR2_PHYERR_ESC 0x0000000f
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#define CSIHOST_ERR2_PHYERR_SOTHS 0x000000f0
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#define CSIHOST_ERR2_ECC_CORRECTED 0x00000f00
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#define CSIHOST_ERR2_ERR_ID 0x0000f000
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#define CSIHOST_ERR2_PHYERR_CODEHS 0x01000000
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#define SW_CPHY_EN(x) ((x) << 0)
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#define SW_DSI_EN(x) ((x) << 4)
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#define SW_DATATYPE_FS(x) ((x) << 8)
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#define SW_DATATYPE_FE(x) ((x) << 14)
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#define SW_DATATYPE_LS(x) ((x) << 20)
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#define SW_DATATYPE_LE(x) ((x) << 26)
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#define RK_MAX_CSI_HW (6)
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/*
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* add new chip id in tail in time order
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* by increasing to distinguish csi2 host version
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*/
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enum rkcsi2_chip_id {
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CHIP_PX30_CSI2,
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CHIP_RK1808_CSI2,
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CHIP_RK3128_CSI2,
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CHIP_RK3288_CSI2,
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CHIP_RV1126_CSI2,
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CHIP_RK3568_CSI2,
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CHIP_RK3588_CSI2,
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CHIP_RV1106_CSI2,
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CHIP_RK3562_CSI2,
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};
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enum csi2_pads {
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RK_CSI2_PAD_SINK = 0,
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RK_CSI2X_PAD_SOURCE0,
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RK_CSI2X_PAD_SOURCE1,
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RK_CSI2X_PAD_SOURCE2,
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RK_CSI2X_PAD_SOURCE3
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};
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enum csi2_err {
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RK_CSI2_ERR_SOTSYN = 0x0,
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RK_CSI2_ERR_FS_FE_MIS,
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RK_CSI2_ERR_FRM_SEQ_ERR,
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RK_CSI2_ERR_CRC_ONCE,
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RK_CSI2_ERR_CRC,
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RK_CSI2_ERR_ALL,
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RK_CSI2_ERR_MAX
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};
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enum host_type_t {
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RK_CSI_RXHOST,
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RK_DSI_RXHOST
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};
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struct csi2_match_data {
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int chip_id;
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int num_pads;
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int num_hw;
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};
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struct csi2_hw_match_data {
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int chip_id;
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};
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struct csi2_sensor_info {
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struct v4l2_subdev *sd;
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struct v4l2_mbus_config mbus;
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int lanes;
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};
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struct csi2_err_stats {
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unsigned int cnt;
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};
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struct csi2_dev {
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struct device *dev;
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struct v4l2_subdev sd;
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struct media_pad pad[CSI2_NUM_PADS_MAX];
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struct clk_bulk_data *clks_bulk;
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int clks_num;
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struct reset_control *rsts_bulk;
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void __iomem *base;
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struct v4l2_async_notifier notifier;
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struct v4l2_fwnode_bus_mipi_csi2 bus;
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/* lock to protect all members below */
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struct mutex lock;
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struct v4l2_mbus_framefmt format_mbus;
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struct v4l2_rect crop;
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int stream_count;
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struct v4l2_subdev *src_sd;
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bool sink_linked[CSI2_NUM_SRC_PADS];
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bool is_check_sot_sync;
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struct csi2_sensor_info sensors[MAX_CSI2_SENSORS];
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const struct csi2_match_data *match_data;
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int num_sensors;
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atomic_t frm_sync_seq;
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struct csi2_err_stats err_list[RK_CSI2_ERR_MAX];
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struct csi2_hw *csi2_hw[RK_MAX_CSI_HW];
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int irq1;
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int irq2;
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int dsi_input_en;
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struct rkcif_csi_info csi_info;
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const char *dev_name;
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};
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struct csi2_hw {
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struct device *dev;
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struct clk_bulk_data *clks_bulk;
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int clks_num;
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struct reset_control *rsts_bulk;
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struct csi2_dev *csi2;
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const struct csi2_hw_match_data *match_data;
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void __iomem *base;
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/* lock to protect all members below */
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struct mutex lock;
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int irq1;
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int irq2;
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const char *dev_name;
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};
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u32 rkcif_csi2_get_sof(struct csi2_dev *csi2_dev);
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void rkcif_csi2_set_sof(struct csi2_dev *csi2_dev, u32 seq);
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void rkcif_csi2_event_inc_sof(struct csi2_dev *csi2_dev);
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int rkcif_csi2_plat_drv_init(void);
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void rkcif_csi2_plat_drv_exit(void);
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int rkcif_csi2_hw_plat_drv_init(void);
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void rkcif_csi2_hw_plat_drv_exit(void);
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int rkcif_csi2_register_notifier(struct notifier_block *nb);
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int rkcif_csi2_unregister_notifier(struct notifier_block *nb);
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void rkcif_csi2_event_reset_pipe(struct csi2_dev *csi2_dev, int reset_src);
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#endif
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