// SPDX-License-Identifier: GPL-2.0
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/*
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* sc035gs driver
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*
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* Copyright (C) 2022 Rockchip Electronics Co., Ltd.
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* V0.1.0: MIPI is ok.
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/sysfs.h>
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#include <linux/slab.h>
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#include <linux/version.h>
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#include <linux/rk-camera-module.h>
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#include <media/media-entity.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-subdev.h>
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#include <linux/pinctrl/consumer.h>
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#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
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#ifndef V4L2_CID_DIGITAL_GAIN
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#define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
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#endif
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#define MIPI_FREQ_180M 180000000
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#define MIPI_FREQ_300M 300000000
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#define PIXEL_RATE_WITH_180M (MIPI_FREQ_180M * 2 / 10 * 2)
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#define PIXEL_RATE_WITH_300M (MIPI_FREQ_300M * 2 / 8 * 1)
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#define SC035GS_XVCLK_FREQ 24000000
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#define CHIP_ID 0x0108
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#define SC132GS_REG_CHIP_ID 0x300A
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#define SC035GS_REG_CTRL_MODE 0x0100
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#define SC035GS_MODE_SW_STANDBY 0x0
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#define SC035GS_MODE_STREAMING BIT(0)
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#define SC035GS_REG_EXPOSURE 0x3e01
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#define SC035GS_EXPOSURE_MIN 6
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#define SC035GS_EXPOSURE_STEP 1
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#define SC035GS_VTS_MAX 0xffff
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#define SC035GS_REG_COARSE_AGAIN 0x3e08
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#define SC035GS_REG_FINE_AGAIN 0x3e09
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#define ANALOG_GAIN_MIN 0x01
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#define ANALOG_GAIN_MAX 0xF8
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#define ANALOG_GAIN_STEP 1
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#define ANALOG_GAIN_DEFAULT 0x1f
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#define SC035GS_REG_TEST_PATTERN 0x4501
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#define SC035GS_TEST_PATTERN_ENABLE 0xcc
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#define SC035GS_TEST_PATTERN_DISABLE 0xc4
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#define SC035GS_REG_VTS 0x320e
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#define REG_NULL 0xFFFF
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#define SC035GS_REG_VALUE_08BIT 1
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#define SC035GS_REG_VALUE_16BIT 2
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#define SC035GS_REG_VALUE_24BIT 3
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#define SC035GS_NAME "sc035gs"
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#define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
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#define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
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static const char *const sc035gs_supply_names[] = {
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"avdd", /* Analog power */
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"dovdd", /* Digital I/O power */
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"dvdd", /* Digital core power */
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};
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#define SC035GS_NUM_SUPPLIES ARRAY_SIZE(sc035gs_supply_names)
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enum {
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LINK_FREQ_180M_INDEX,
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LINK_FREQ_300M_INDEX,
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};
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struct regval {
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u16 addr;
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u8 val;
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};
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struct sc035gs_mode {
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u32 width;
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u32 height;
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struct v4l2_fract max_fps;
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u32 hts_def;
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u32 vts_def;
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u32 exp_def;
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u32 link_freq_index;
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u64 pixel_rate;
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const struct regval *reg_list;
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u32 lanes;
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u32 bus_fmt;
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};
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struct sc035gs {
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struct i2c_client *client;
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struct clk *xvclk;
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struct gpio_desc *reset_gpio;
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struct gpio_desc *pwdn_gpio;
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struct regulator_bulk_data supplies[SC035GS_NUM_SUPPLIES];
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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struct pinctrl_state *pins_sleep;
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struct v4l2_subdev subdev;
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struct media_pad pad;
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struct v4l2_ctrl_handler ctrl_handler;
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struct v4l2_ctrl *exposure;
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struct v4l2_ctrl *anal_gain;
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struct v4l2_ctrl *digi_gain;
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struct v4l2_ctrl *hblank;
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struct v4l2_ctrl *vblank;
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struct v4l2_ctrl *test_pattern;
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struct v4l2_ctrl *pixel_rate;
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struct v4l2_ctrl *link_freq;
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struct mutex mutex;
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struct v4l2_fract cur_fps;
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u32 cur_vts;
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bool streaming;
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bool power_on;
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const struct sc035gs_mode *cur_mode;
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u32 module_index;
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const char *module_facing;
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const char *module_name;
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const char *len_name;
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};
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#define to_sc035gs(sd) container_of(sd, struct sc035gs, subdev)
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/*
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* Xclk 24Mhz
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* Pclk 72Mhz
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* linelength 1600(0x06a0)
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* framelength 1250(0x04e2)
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* grabwindow_width 640
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* grabwindow_height 480
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* mipi 2 lane
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* max_framerate 30fps
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* mipi_datarate per lane 360Mbps
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*/
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static const struct regval sc035gs_2lane_10bit_regs[] = {
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{0x0103, 0x01},
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{0x0100, 0x00},
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{0x36e9, 0x80},
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{0x36f9, 0x80},
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{0x3000, 0x00},
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{0x3001, 0x00},
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{0x300f, 0x0f},
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{0x3018, 0x33},
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{0x3019, 0xfc},
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{0x301c, 0x78},
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{0x301f, 0x9c},
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{0x3031, 0x0a},
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{0x3037, 0x20},
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{0x303f, 0x01},
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{0x320c, 0x06},
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{0x320d, 0x40},
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{0x320e, 0x04},
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{0x320f, 0xe2},
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{0x3217, 0x00},
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{0x3218, 0x00},
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{0x3220, 0x10},
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{0x3223, 0x48},
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{0x3226, 0x74},
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{0x3227, 0x07},
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{0x323b, 0x00},
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{0x3250, 0xf0},
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{0x3251, 0x02},
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{0x3252, 0x02},
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{0x3253, 0x08},
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{0x3254, 0x02},
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{0x3255, 0x07},
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{0x3304, 0x48},
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{0x3305, 0x00},
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{0x3306, 0x98},
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{0x3309, 0x50},
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{0x330a, 0x01},
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{0x330b, 0x18},
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{0x330c, 0x18},
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{0x330f, 0x40},
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{0x3310, 0x10},
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{0x3314, 0x68},
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{0x3315, 0x30},
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{0x3316, 0x68},
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{0x3317, 0x14},
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{0x3329, 0x5c},
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{0x332d, 0x5c},
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{0x332f, 0x60},
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{0x3335, 0x64},
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{0x3344, 0x64},
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{0x335b, 0x80},
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{0x335f, 0x80},
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{0x3366, 0x06},
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{0x3385, 0x41},
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{0x3387, 0x49},
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{0x3389, 0x01},
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{0x33b1, 0x03},
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{0x33b2, 0x06},
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{0x33bd, 0xe0},
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{0x33bf, 0x10},
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{0x3621, 0xa4},
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{0x3622, 0x05},
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{0x3624, 0x47},
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{0x3630, 0x4a},
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{0x3631, 0x58},
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{0x3633, 0x52},
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{0x3635, 0x03},
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{0x3636, 0x25},
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{0x3637, 0x8a},
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{0x3638, 0x0f},
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{0x3639, 0x08},
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{0x363a, 0x00},
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{0x363b, 0x48},
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{0x363c, 0x86},
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{0x363e, 0xf8},
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{0x3640, 0x00},
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{0x3641, 0x01},
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{0x36ea, 0x3b},
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{0x36eb, 0x0e},
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{0x36ec, 0x1e},
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{0x36ed, 0x20},
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{0x36fa, 0x3b},
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{0x36fb, 0x10},
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{0x36fc, 0x02},
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{0x36fd, 0x00},
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{0x3908, 0x91},
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{0x391b, 0x81},
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{0x3d08, 0x01},
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{0x3e01, 0x18},
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{0x3e02, 0xf0},
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{0x3f04, 0x06},
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{0x3f05, 0x20},
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{0x4500, 0x59},
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{0x4501, 0xc4},
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{0x4603, 0x00},
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{0x4800, 0x64},
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{0x4809, 0x01},
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{0x4810, 0x00},
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{0x4811, 0x01},
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{0x4837, 0x42},
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{0x5011, 0x00},
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{0x5988, 0x02},
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{0x598e, 0x06},
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{0x598f, 0x08},
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{0x36e9, 0x24},
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{0x36f9, 0x24},
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//again adjust
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{0x4418, 0x0a},
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{0x363d, 0x10},
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{0x4419, 0x80},
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//mirror & flip
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{0x3221, (0x03 << 1)},
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//exposure 5ms
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{0x3e01, 0x13},
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{0x3e02, 0xc0},
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//dgain 1
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{0x3e06, 0x0c},
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{0x3e07, 0x80},
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//gain < 2
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{0x3631, 0x58},
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{0x3630, 0x4a},
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//again 1
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{0x3e08, 0x03},
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{0x3e09, 0x10},
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{REG_NULL, 0x00},
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};
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static const struct sc035gs_mode supported_modes[] = {
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{
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.width = 640,
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.height = 480,
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.max_fps = {
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.numerator = 10000,
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.denominator = 300000,
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},
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.exp_def = 0x0bb,
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.hts_def = 0x640,
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.vts_def = 0x4e2,
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.link_freq_index = LINK_FREQ_300M_INDEX,
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.pixel_rate = PIXEL_RATE_WITH_300M,
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.reg_list = sc035gs_2lane_10bit_regs,
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.lanes = 2,
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.bus_fmt = MEDIA_BUS_FMT_Y10_1X10,
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},
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};
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static const char *const sc035gs_test_pattern_menu[] = {
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"Disabled",
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"Vertical Color Bar Type 1",
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"Vertical Color Bar Type 2",
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"Vertical Color Bar Type 3",
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"Vertical Color Bar Type 4"
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};
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static const s64 link_freq_menu_items[] = {
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MIPI_FREQ_180M,
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MIPI_FREQ_300M,
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};
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/* Write registers up to 4 at a time */
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static int sc035gs_write_reg(struct i2c_client *client,
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u16 reg, u32 len, u32 val)
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{
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u32 buf_i, val_i;
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u8 buf[6];
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u8 *val_p;
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__be32 val_be;
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u32 ret;
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if (len > 4)
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return -EINVAL;
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buf[0] = reg >> 8;
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buf[1] = reg & 0xff;
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val_be = cpu_to_be32(val);
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val_p = (u8 *)&val_be;
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buf_i = 2;
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val_i = 4 - len;
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while (val_i < 4)
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buf[buf_i++] = val_p[val_i++];
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ret = i2c_master_send(client, buf, len + 2);
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if (ret != len + 2)
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return -EIO;
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return 0;
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}
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static int sc035gs_write_array(struct i2c_client *client,
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const struct regval *regs)
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{
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u32 i;
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int ret = 0;
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for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
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ret = sc035gs_write_reg(client, regs[i].addr,
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SC035GS_REG_VALUE_08BIT, regs[i].val);
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}
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return ret;
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}
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/* Read registers up to 4 at a time */
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static int sc035gs_read_reg(struct i2c_client *client,
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u16 reg, unsigned int len, u32 *val)
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{
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struct i2c_msg msgs[2];
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u8 *data_be_p;
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__be32 data_be = 0;
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__be16 reg_addr_be = cpu_to_be16(reg);
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int ret;
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if (len > 4 || !len)
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return -EINVAL;
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data_be_p = (u8 *)&data_be;
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/* Write register address */
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msgs[0].addr = client->addr;
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msgs[0].flags = 0;
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msgs[0].len = 2;
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msgs[0].buf = (u8 *)®_addr_be;
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/* Read data from register */
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msgs[1].addr = client->addr;
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msgs[1].flags = I2C_M_RD;
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msgs[1].len = len;
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msgs[1].buf = &data_be_p[4 - len];
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ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
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if (ret != ARRAY_SIZE(msgs))
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return -EIO;
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*val = be32_to_cpu(data_be);
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return 0;
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}
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static int sc035gs_get_reso_dist(const struct sc035gs_mode *mode,
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struct v4l2_mbus_framefmt *framefmt)
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{
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return abs(mode->width - framefmt->width) +
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abs(mode->height - framefmt->height);
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}
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static const struct sc035gs_mode *
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sc035gs_find_best_fit(struct v4l2_subdev_format *fmt)
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{
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struct v4l2_mbus_framefmt *framefmt = &fmt->format;
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int dist;
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int cur_best_fit = 0;
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int cur_best_fit_dist = -1;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
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dist = sc035gs_get_reso_dist(&supported_modes[i], framefmt);
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if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
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(supported_modes[i].bus_fmt == framefmt->code)) {
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cur_best_fit_dist = dist;
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cur_best_fit = i;
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}
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}
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return &supported_modes[cur_best_fit];
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}
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static int sc035gs_set_fmt(struct v4l2_subdev *sd,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_format *fmt)
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{
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struct sc035gs *sc035gs = to_sc035gs(sd);
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const struct sc035gs_mode *mode;
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s64 h_blank, vblank_def;
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mutex_lock(&sc035gs->mutex);
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mode = sc035gs_find_best_fit(fmt);
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fmt->format.code = mode->bus_fmt;
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fmt->format.width = mode->width;
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fmt->format.height = mode->height;
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fmt->format.field = V4L2_FIELD_NONE;
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if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
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#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
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*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
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#else
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mutex_unlock(&sc035gs->mutex);
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return -ENOTTY;
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#endif
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} else {
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sc035gs->cur_mode = mode;
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h_blank = mode->hts_def - mode->width;
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__v4l2_ctrl_modify_range(sc035gs->hblank, h_blank,
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h_blank, 1, h_blank);
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vblank_def = mode->vts_def - mode->height;
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__v4l2_ctrl_modify_range(sc035gs->vblank, vblank_def,
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SC035GS_VTS_MAX - mode->height,
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1, vblank_def);
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__v4l2_ctrl_s_ctrl_int64(sc035gs->pixel_rate, mode->pixel_rate);
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__v4l2_ctrl_s_ctrl(sc035gs->link_freq, mode->link_freq_index);
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sc035gs->cur_vts = mode->vts_def;
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sc035gs->cur_fps = mode->max_fps;
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}
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mutex_unlock(&sc035gs->mutex);
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return 0;
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}
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static int sc035gs_get_fmt(struct v4l2_subdev *sd,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_format *fmt)
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{
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struct sc035gs *sc035gs = to_sc035gs(sd);
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const struct sc035gs_mode *mode = sc035gs->cur_mode;
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mutex_lock(&sc035gs->mutex);
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if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
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#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
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fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
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#else
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mutex_unlock(&sc035gs->mutex);
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return -ENOTTY;
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#endif
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} else {
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fmt->format.width = mode->width;
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fmt->format.height = mode->height;
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fmt->format.code = mode->bus_fmt;
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fmt->format.field = V4L2_FIELD_NONE;
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}
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mutex_unlock(&sc035gs->mutex);
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return 0;
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}
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static int sc035gs_enum_mbus_code(struct v4l2_subdev *sd,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_mbus_code_enum *code)
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{
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struct sc035gs *sc035gs = to_sc035gs(sd);
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if (code->index != 0)
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return -EINVAL;
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code->code = sc035gs->cur_mode->bus_fmt;
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return 0;
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}
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static int sc035gs_enum_frame_sizes(struct v4l2_subdev *sd,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_frame_size_enum *fse)
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{
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if (fse->index >= ARRAY_SIZE(supported_modes))
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return -EINVAL;
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if (fse->code != supported_modes[fse->index].bus_fmt)
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return -EINVAL;
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fse->min_width = supported_modes[fse->index].width;
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fse->max_width = supported_modes[fse->index].width;
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fse->max_height = supported_modes[fse->index].height;
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fse->min_height = supported_modes[fse->index].height;
|
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return 0;
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}
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static int sc035gs_enable_test_pattern(struct sc035gs *sc035gs, u32 pattern)
|
{
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u32 val;
|
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if (pattern)
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val = (pattern - 1) | SC035GS_TEST_PATTERN_ENABLE;
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else
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val = SC035GS_TEST_PATTERN_DISABLE;
|
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return sc035gs_write_reg(sc035gs->client, SC035GS_REG_TEST_PATTERN,
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SC035GS_REG_VALUE_08BIT, val);
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}
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static void sc035gs_get_module_inf(struct sc035gs *sc035gs,
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struct rkmodule_inf *inf)
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{
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memset(inf, 0, sizeof(*inf));
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strscpy(inf->base.sensor, SC035GS_NAME, sizeof(inf->base.sensor));
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strscpy(inf->base.module, sc035gs->module_name,
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sizeof(inf->base.module));
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strscpy(inf->base.lens, sc035gs->len_name, sizeof(inf->base.lens));
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}
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static long sc035gs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
|
{
|
struct sc035gs *sc035gs = to_sc035gs(sd);
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long ret = 0;
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u32 stream = 0;
|
|
switch (cmd) {
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case RKMODULE_GET_MODULE_INFO:
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sc035gs_get_module_inf(sc035gs, (struct rkmodule_inf *)arg);
|
break;
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case RKMODULE_SET_QUICK_STREAM:
|
|
stream = *((u32 *)arg);
|
|
if (stream)
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ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
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SC035GS_REG_VALUE_08BIT, SC035GS_MODE_STREAMING);
|
else
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ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
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SC035GS_REG_VALUE_08BIT, SC035GS_MODE_SW_STANDBY);
|
break;
|
default:
|
ret = -ENOIOCTLCMD;
|
break;
|
}
|
|
return ret;
|
}
|
|
#ifdef CONFIG_COMPAT
|
static long sc035gs_compat_ioctl32(struct v4l2_subdev *sd,
|
unsigned int cmd, unsigned long arg)
|
{
|
void __user *up = compat_ptr(arg);
|
struct rkmodule_inf *inf;
|
long ret = 0;
|
u32 stream = 0;
|
|
switch (cmd) {
|
case RKMODULE_GET_MODULE_INFO:
|
inf = kzalloc(sizeof(*inf), GFP_KERNEL);
|
if (!inf) {
|
ret = -ENOMEM;
|
return ret;
|
}
|
|
ret = sc035gs_ioctl(sd, cmd, inf);
|
if (!ret) {
|
ret = copy_to_user(up, inf, sizeof(*inf));
|
if (ret)
|
ret = -EFAULT;
|
}
|
kfree(inf);
|
break;
|
case RKMODULE_SET_QUICK_STREAM:
|
if (copy_from_user(&stream, up, sizeof(u32)))
|
return -EFAULT;
|
|
ret = sc035gs_ioctl(sd, cmd, &stream);
|
break;
|
default:
|
ret = -ENOIOCTLCMD;
|
break;
|
}
|
|
return ret;
|
}
|
#endif
|
|
static int sc035gs_set_ctrl_gain(struct sc035gs *sc035gs, u32 a_gain)
|
{
|
int ret = 0;
|
u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg;
|
|
/* (1.0 - 15.5) * 0x10 (fix point) */
|
if (a_gain < 0x10)
|
a_gain = 0x10;
|
if (a_gain > 0xf8)
|
a_gain = 0xf8;
|
|
if (a_gain < 0x20) { /*1x ~ 2x*/
|
coarse_again = 0x3;
|
fine_again = a_gain * 16 / 0x10;
|
} else if (a_gain < 0x40) { /*2x ~ 4x*/
|
coarse_again = 0x7;
|
fine_again = a_gain * 8 / 0x10;
|
} else if (a_gain < 0x80) { /*4x ~ 8x*/
|
coarse_again = 0xf;
|
fine_again = a_gain * 4 / 0x10;
|
} else { /*8x ~ 16x*/
|
coarse_again = 0x1f;
|
fine_again = a_gain * 2 / 0x10;
|
}
|
|
fine_again_reg = fine_again & 0x1F;
|
coarse_again_reg = coarse_again & 0x1F;
|
|
if (a_gain < 0x20) {
|
ret |= sc035gs_write_reg(sc035gs->client, 0x3631,
|
SC035GS_REG_VALUE_08BIT, 0x58);
|
ret |= sc035gs_write_reg(sc035gs->client, 0x3630,
|
SC035GS_REG_VALUE_08BIT, 0x4a);
|
} else {
|
ret |= sc035gs_write_reg(sc035gs->client, 0x3631,
|
SC035GS_REG_VALUE_08BIT, 0x48);
|
ret |= sc035gs_write_reg(sc035gs->client, 0x3630,
|
SC035GS_REG_VALUE_08BIT, 0x4c);
|
}
|
|
ret |= sc035gs_write_reg(sc035gs->client,
|
SC035GS_REG_COARSE_AGAIN,
|
SC035GS_REG_VALUE_08BIT,
|
coarse_again_reg);
|
ret |= sc035gs_write_reg(sc035gs->client,
|
SC035GS_REG_FINE_AGAIN,
|
SC035GS_REG_VALUE_08BIT,
|
fine_again_reg);
|
|
return ret;
|
}
|
|
|
static int __sc035gs_start_stream(struct sc035gs *sc035gs)
|
{
|
int ret;
|
|
ret = sc035gs_write_array(sc035gs->client, sc035gs->cur_mode->reg_list);
|
if (ret)
|
return ret;
|
|
/* In case these controls are set before streaming */
|
mutex_unlock(&sc035gs->mutex);
|
ret = v4l2_ctrl_handler_setup(&sc035gs->ctrl_handler);
|
mutex_lock(&sc035gs->mutex);
|
if (ret)
|
return ret;
|
|
ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
|
SC035GS_REG_VALUE_08BIT, SC035GS_MODE_STREAMING);
|
|
usleep_range(10000, 12000);
|
|
ret |= sc035gs_write_reg(sc035gs->client, 0x4418,
|
SC035GS_REG_VALUE_08BIT, 0x0a);
|
ret |= sc035gs_write_reg(sc035gs->client, 0x4419,
|
SC035GS_REG_VALUE_08BIT, 0x80);
|
return ret;
|
}
|
|
static int __sc035gs_stop_stream(struct sc035gs *sc035gs)
|
{
|
return sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
|
SC035GS_REG_VALUE_08BIT, SC035GS_MODE_SW_STANDBY);
|
}
|
|
static int sc035gs_s_stream(struct v4l2_subdev *sd, int on)
|
{
|
struct sc035gs *sc035gs = to_sc035gs(sd);
|
struct i2c_client *client = sc035gs->client;
|
unsigned int fps;
|
int ret = 0;
|
|
mutex_lock(&sc035gs->mutex);
|
on = !!on;
|
if (on == sc035gs->streaming)
|
goto unlock_and_return;
|
|
fps = DIV_ROUND_CLOSEST(sc035gs->cur_mode->max_fps.denominator,
|
sc035gs->cur_mode->max_fps.numerator);
|
|
dev_info(&sc035gs->client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
|
sc035gs->cur_mode->width,
|
sc035gs->cur_mode->height,
|
fps);
|
|
if (on) {
|
ret = pm_runtime_get_sync(&client->dev);
|
if (ret < 0) {
|
pm_runtime_put_noidle(&client->dev);
|
goto unlock_and_return;
|
}
|
|
ret = __sc035gs_start_stream(sc035gs);
|
if (ret) {
|
v4l2_err(sd, "start stream failed while write regs\n");
|
pm_runtime_put(&client->dev);
|
goto unlock_and_return;
|
}
|
} else {
|
__sc035gs_stop_stream(sc035gs);
|
pm_runtime_put(&client->dev);
|
}
|
|
sc035gs->streaming = on;
|
|
unlock_and_return:
|
mutex_unlock(&sc035gs->mutex);
|
|
return ret;
|
}
|
|
static int sc035gs_s_power(struct v4l2_subdev *sd, int on)
|
{
|
struct sc035gs *sc035gs = to_sc035gs(sd);
|
struct i2c_client *client = sc035gs->client;
|
int ret = 0;
|
|
mutex_lock(&sc035gs->mutex);
|
|
/* If the power state is not modified - no work to do. */
|
if (sc035gs->power_on == !!on)
|
goto unlock_and_return;
|
|
if (on) {
|
ret = pm_runtime_get_sync(&client->dev);
|
if (ret < 0) {
|
pm_runtime_put_noidle(&client->dev);
|
goto unlock_and_return;
|
}
|
sc035gs->power_on = true;
|
} else {
|
pm_runtime_put(&client->dev);
|
sc035gs->power_on = false;
|
}
|
|
unlock_and_return:
|
mutex_unlock(&sc035gs->mutex);
|
|
return ret;
|
}
|
|
static int sc035gs_g_frame_interval(struct v4l2_subdev *sd,
|
struct v4l2_subdev_frame_interval *fi)
|
{
|
struct sc035gs *sc035gs = to_sc035gs(sd);
|
const struct sc035gs_mode *mode = sc035gs->cur_mode;
|
|
if (sc035gs->streaming)
|
fi->interval = sc035gs->cur_fps;
|
else
|
fi->interval = mode->max_fps;
|
|
return 0;
|
}
|
|
/* Calculate the delay in us by clock rate and clock cycles */
|
static inline u32 sc035gs_cal_delay(u32 cycles)
|
{
|
return DIV_ROUND_UP(cycles, SC035GS_XVCLK_FREQ / 1000 / 1000);
|
}
|
|
static int __sc035gs_power_on(struct sc035gs *sc035gs)
|
{
|
int ret;
|
u32 delay_us;
|
struct device *dev = &sc035gs->client->dev;
|
|
if (!IS_ERR_OR_NULL(sc035gs->pins_default)) {
|
ret = pinctrl_select_state(sc035gs->pinctrl,
|
sc035gs->pins_default);
|
if (ret < 0)
|
dev_err(dev, "could not set pins\n");
|
}
|
|
ret = clk_set_rate(sc035gs->xvclk, SC035GS_XVCLK_FREQ);
|
if (ret < 0)
|
dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
|
if (clk_get_rate(sc035gs->xvclk) != SC035GS_XVCLK_FREQ)
|
dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
|
ret = clk_prepare_enable(sc035gs->xvclk);
|
if (ret < 0) {
|
dev_err(dev, "Failed to enable xvclk\n");
|
return ret;
|
}
|
|
ret = regulator_bulk_enable(SC035GS_NUM_SUPPLIES, sc035gs->supplies);
|
if (ret < 0) {
|
dev_err(dev, "Failed to enable regulators\n");
|
goto disable_clk;
|
}
|
|
if (!IS_ERR(sc035gs->reset_gpio))
|
gpiod_set_value_cansleep(sc035gs->reset_gpio, 1);
|
|
usleep_range(1000, 2000);
|
|
if (!IS_ERR(sc035gs->pwdn_gpio))
|
gpiod_set_value_cansleep(sc035gs->pwdn_gpio, 1);
|
|
if (!IS_ERR(sc035gs->reset_gpio))
|
gpiod_set_value_cansleep(sc035gs->reset_gpio, 0);
|
|
/* 8192 cycles prior to first SCCB transaction */
|
delay_us = sc035gs_cal_delay(8192);
|
usleep_range(delay_us, delay_us * 2);
|
|
return 0;
|
|
disable_clk:
|
clk_disable_unprepare(sc035gs->xvclk);
|
|
return ret;
|
}
|
|
static void __sc035gs_power_off(struct sc035gs *sc035gs)
|
{
|
int ret;
|
|
if (!IS_ERR(sc035gs->reset_gpio))
|
gpiod_set_value_cansleep(sc035gs->reset_gpio, 1);
|
|
if (!IS_ERR(sc035gs->pwdn_gpio))
|
gpiod_set_value_cansleep(sc035gs->pwdn_gpio, 0);
|
clk_disable_unprepare(sc035gs->xvclk);
|
if (!IS_ERR_OR_NULL(sc035gs->pins_sleep)) {
|
ret = pinctrl_select_state(sc035gs->pinctrl,
|
sc035gs->pins_sleep);
|
if (ret < 0)
|
dev_dbg(&sc035gs->client->dev, "could not set pins\n");
|
}
|
regulator_bulk_disable(SC035GS_NUM_SUPPLIES, sc035gs->supplies);
|
}
|
|
static int sc035gs_runtime_resume(struct device *dev)
|
{
|
struct i2c_client *client = to_i2c_client(dev);
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
struct sc035gs *sc035gs = to_sc035gs(sd);
|
|
return __sc035gs_power_on(sc035gs);
|
}
|
|
static int sc035gs_runtime_suspend(struct device *dev)
|
{
|
struct i2c_client *client = to_i2c_client(dev);
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
struct sc035gs *sc035gs = to_sc035gs(sd);
|
|
__sc035gs_power_off(sc035gs);
|
|
return 0;
|
}
|
|
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
static int sc035gs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
|
{
|
struct sc035gs *sc035gs = to_sc035gs(sd);
|
struct v4l2_mbus_framefmt *try_fmt =
|
v4l2_subdev_get_try_format(sd, fh->pad, 0);
|
const struct sc035gs_mode *def_mode = &supported_modes[0];
|
|
mutex_lock(&sc035gs->mutex);
|
/* Initialize try_fmt */
|
try_fmt->width = def_mode->width;
|
try_fmt->height = def_mode->height;
|
try_fmt->code = def_mode->bus_fmt;
|
try_fmt->field = V4L2_FIELD_NONE;
|
|
mutex_unlock(&sc035gs->mutex);
|
/* No crop or compose */
|
|
return 0;
|
}
|
#endif
|
|
static int sc035gs_enum_frame_interval(struct v4l2_subdev *sd,
|
struct v4l2_subdev_pad_config *cfg,
|
struct v4l2_subdev_frame_interval_enum *fie)
|
{
|
if (fie->index >= ARRAY_SIZE(supported_modes))
|
return -EINVAL;
|
|
fie->code = supported_modes[fie->index].bus_fmt;
|
fie->width = supported_modes[fie->index].width;
|
fie->height = supported_modes[fie->index].height;
|
fie->interval = supported_modes[fie->index].max_fps;
|
return 0;
|
}
|
|
static int sc035gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
|
struct v4l2_mbus_config *config)
|
{
|
u32 val = 0;
|
struct sc035gs *sc035gs = to_sc035gs(sd);
|
|
val = 1 << (sc035gs->cur_mode->lanes - 1) |
|
V4L2_MBUS_CSI2_CHANNEL_0 |
|
V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
|
config->type = V4L2_MBUS_CSI2_DPHY;
|
config->flags = val;
|
|
return 0;
|
}
|
|
static const struct dev_pm_ops sc035gs_pm_ops = {
|
SET_RUNTIME_PM_OPS(sc035gs_runtime_suspend,
|
sc035gs_runtime_resume, NULL)
|
};
|
|
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
static const struct v4l2_subdev_internal_ops sc035gs_internal_ops = {
|
.open = sc035gs_open,
|
};
|
#endif
|
|
static const struct v4l2_subdev_core_ops sc035gs_core_ops = {
|
.s_power = sc035gs_s_power,
|
.ioctl = sc035gs_ioctl,
|
#ifdef CONFIG_COMPAT
|
.compat_ioctl32 = sc035gs_compat_ioctl32,
|
#endif
|
};
|
|
static const struct v4l2_subdev_video_ops sc035gs_video_ops = {
|
.s_stream = sc035gs_s_stream,
|
.g_frame_interval = sc035gs_g_frame_interval,
|
};
|
|
static const struct v4l2_subdev_pad_ops sc035gs_pad_ops = {
|
.enum_mbus_code = sc035gs_enum_mbus_code,
|
.enum_frame_size = sc035gs_enum_frame_sizes,
|
.enum_frame_interval = sc035gs_enum_frame_interval,
|
.get_fmt = sc035gs_get_fmt,
|
.set_fmt = sc035gs_set_fmt,
|
.get_mbus_config = sc035gs_g_mbus_config,
|
};
|
|
static const struct v4l2_subdev_ops sc035gs_subdev_ops = {
|
.core = &sc035gs_core_ops,
|
.video = &sc035gs_video_ops,
|
.pad = &sc035gs_pad_ops,
|
};
|
|
static void sc035gs_modify_fps_info(struct sc035gs *sc035gs)
|
{
|
const struct sc035gs_mode *mode = sc035gs->cur_mode;
|
|
sc035gs->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
|
sc035gs->cur_vts;
|
}
|
|
static int sc035gs_set_ctrl(struct v4l2_ctrl *ctrl)
|
{
|
struct sc035gs *sc035gs = container_of(ctrl->handler,
|
struct sc035gs, ctrl_handler);
|
struct i2c_client *client = sc035gs->client;
|
s64 max;
|
int ret = 0;
|
|
/* Propagate change of current control to all related controls */
|
switch (ctrl->id) {
|
case V4L2_CID_VBLANK:
|
/* Update max exposure while meeting expected vblanking */
|
max = sc035gs->cur_mode->height + ctrl->val - 6;
|
__v4l2_ctrl_modify_range(sc035gs->exposure,
|
sc035gs->exposure->minimum, max,
|
sc035gs->exposure->step,
|
sc035gs->exposure->default_value);
|
break;
|
}
|
|
if (!pm_runtime_get_if_in_use(&client->dev))
|
return 0;
|
|
switch (ctrl->id) {
|
case V4L2_CID_EXPOSURE:
|
/* 4 least significant bits of expsoure are fractional part */
|
ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_EXPOSURE,
|
SC035GS_REG_VALUE_16BIT, ctrl->val << 4);
|
break;
|
case V4L2_CID_ANALOGUE_GAIN:
|
ret = sc035gs_set_ctrl_gain(sc035gs, ctrl->val);
|
break;
|
case V4L2_CID_VBLANK:
|
ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_VTS,
|
SC035GS_REG_VALUE_16BIT,
|
ctrl->val + sc035gs->cur_mode->height);
|
if (!ret)
|
sc035gs->cur_vts = ctrl->val + sc035gs->cur_mode->height;
|
sc035gs_modify_fps_info(sc035gs);
|
break;
|
case V4L2_CID_TEST_PATTERN:
|
ret = sc035gs_enable_test_pattern(sc035gs, ctrl->val);
|
break;
|
default:
|
dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
|
__func__, ctrl->id, ctrl->val);
|
break;
|
}
|
|
pm_runtime_put(&client->dev);
|
|
return ret;
|
}
|
|
static const struct v4l2_ctrl_ops sc035gs_ctrl_ops = {
|
.s_ctrl = sc035gs_set_ctrl,
|
};
|
|
static int sc035gs_initialize_controls(struct sc035gs *sc035gs)
|
{
|
const struct sc035gs_mode *mode;
|
struct v4l2_ctrl_handler *handler;
|
s64 exposure_max, vblank_def;
|
u32 h_blank;
|
int ret;
|
|
handler = &sc035gs->ctrl_handler;
|
mode = sc035gs->cur_mode;
|
ret = v4l2_ctrl_handler_init(handler, 8);
|
if (ret)
|
return ret;
|
handler->lock = &sc035gs->mutex;
|
|
sc035gs->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
|
ARRAY_SIZE(link_freq_menu_items) - 1, 0,
|
link_freq_menu_items);
|
|
sc035gs->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
|
V4L2_CID_PIXEL_RATE,
|
0, PIXEL_RATE_WITH_300M,
|
1, mode->pixel_rate);
|
|
__v4l2_ctrl_s_ctrl(sc035gs->link_freq, mode->pixel_rate);
|
|
h_blank = mode->hts_def - mode->width;
|
sc035gs->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
|
h_blank, h_blank, 1, h_blank);
|
if (sc035gs->hblank)
|
sc035gs->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
|
|
vblank_def = mode->vts_def - mode->height;
|
sc035gs->cur_vts = mode->vts_def;
|
sc035gs->cur_fps = mode->max_fps;
|
sc035gs->vblank = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
|
V4L2_CID_VBLANK, vblank_def,
|
SC035GS_VTS_MAX - mode->height,
|
1, vblank_def);
|
|
exposure_max = mode->vts_def - 6;
|
sc035gs->exposure = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
|
V4L2_CID_EXPOSURE, SC035GS_EXPOSURE_MIN,
|
exposure_max, SC035GS_EXPOSURE_STEP,
|
mode->exp_def);
|
|
sc035gs->anal_gain = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
|
V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
|
ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
|
ANALOG_GAIN_DEFAULT);
|
|
sc035gs->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
|
&sc035gs_ctrl_ops, V4L2_CID_TEST_PATTERN,
|
ARRAY_SIZE(sc035gs_test_pattern_menu) - 1,
|
0, 0, sc035gs_test_pattern_menu);
|
|
if (handler->error) {
|
ret = handler->error;
|
dev_err(&sc035gs->client->dev,
|
"Failed to init controls(%d)\n", ret);
|
goto err_free_handler;
|
}
|
|
sc035gs->subdev.ctrl_handler = handler;
|
|
return 0;
|
|
err_free_handler:
|
v4l2_ctrl_handler_free(handler);
|
|
return ret;
|
}
|
|
static int sc035gs_check_sensor_id(struct sc035gs *sc035gs,
|
struct i2c_client *client)
|
{
|
struct device *dev = &sc035gs->client->dev;
|
u32 id = 0;
|
int ret;
|
|
ret = sc035gs_read_reg(client, SC132GS_REG_CHIP_ID,
|
SC035GS_REG_VALUE_16BIT, &id);
|
if (ret || id != CHIP_ID) {
|
dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
|
return -ENODEV;
|
}
|
|
dev_info(dev, "Detected SC035GS CHIP ID = 0x%04x sensor\n", CHIP_ID);
|
|
return 0;
|
}
|
|
static int sc035gs_configure_regulators(struct sc035gs *sc035gs)
|
{
|
unsigned int i;
|
|
for (i = 0; i < SC035GS_NUM_SUPPLIES; i++)
|
sc035gs->supplies[i].supply = sc035gs_supply_names[i];
|
|
return devm_regulator_bulk_get(&sc035gs->client->dev,
|
SC035GS_NUM_SUPPLIES,
|
sc035gs->supplies);
|
}
|
|
static int sc035gs_probe(struct i2c_client *client,
|
const struct i2c_device_id *id)
|
{
|
struct device *dev = &client->dev;
|
struct device_node *node = dev->of_node;
|
struct sc035gs *sc035gs;
|
struct v4l2_subdev *sd;
|
char facing[2];
|
int ret;
|
|
dev_info(dev, "driver version: %02x.%02x.%02x",
|
DRIVER_VERSION >> 16,
|
(DRIVER_VERSION & 0xff00) >> 8,
|
DRIVER_VERSION & 0x00ff);
|
|
sc035gs = devm_kzalloc(dev, sizeof(*sc035gs), GFP_KERNEL);
|
if (!sc035gs)
|
return -ENOMEM;
|
|
ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
|
&sc035gs->module_index);
|
ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
|
&sc035gs->module_facing);
|
ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
|
&sc035gs->module_name);
|
ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
|
&sc035gs->len_name);
|
if (ret) {
|
dev_err(dev, "could not get module information!\n");
|
return -EINVAL;
|
}
|
sc035gs->client = client;
|
sc035gs->cur_mode = &supported_modes[0];
|
|
sc035gs->xvclk = devm_clk_get(dev, "xvclk");
|
if (IS_ERR(sc035gs->xvclk)) {
|
dev_err(dev, "Failed to get xvclk\n");
|
return -EINVAL;
|
}
|
|
sc035gs->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
|
if (IS_ERR(sc035gs->reset_gpio))
|
dev_warn(dev, "Failed to get reset-gpios\n");
|
|
sc035gs->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
|
if (IS_ERR(sc035gs->pwdn_gpio))
|
dev_warn(dev, "Failed to get pwdn-gpios\n");
|
ret = sc035gs_configure_regulators(sc035gs);
|
if (ret) {
|
dev_err(dev, "Failed to get power regulators\n");
|
return ret;
|
}
|
|
sc035gs->pinctrl = devm_pinctrl_get(dev);
|
if (!IS_ERR(sc035gs->pinctrl)) {
|
sc035gs->pins_default =
|
pinctrl_lookup_state(sc035gs->pinctrl,
|
OF_CAMERA_PINCTRL_STATE_DEFAULT);
|
if (IS_ERR(sc035gs->pins_default))
|
dev_err(dev, "could not get default pinstate\n");
|
|
sc035gs->pins_sleep =
|
pinctrl_lookup_state(sc035gs->pinctrl,
|
OF_CAMERA_PINCTRL_STATE_SLEEP);
|
if (IS_ERR(sc035gs->pins_sleep))
|
dev_err(dev, "could not get sleep pinstate\n");
|
}
|
mutex_init(&sc035gs->mutex);
|
|
sd = &sc035gs->subdev;
|
v4l2_i2c_subdev_init(sd, client, &sc035gs_subdev_ops);
|
ret = sc035gs_initialize_controls(sc035gs);
|
if (ret)
|
goto err_destroy_mutex;
|
|
ret = __sc035gs_power_on(sc035gs);
|
if (ret)
|
goto err_free_handler;
|
|
ret = sc035gs_check_sensor_id(sc035gs, client);
|
if (ret)
|
goto err_power_off;
|
|
#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
|
sd->internal_ops = &sc035gs_internal_ops;
|
sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
|
V4L2_SUBDEV_FL_HAS_EVENTS;
|
#endif
|
#if defined(CONFIG_MEDIA_CONTROLLER)
|
sc035gs->pad.flags = MEDIA_PAD_FL_SOURCE;
|
sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
|
ret = media_entity_pads_init(&sd->entity, 1, &sc035gs->pad);
|
if (ret < 0)
|
goto err_power_off;
|
#endif
|
|
memset(facing, 0, sizeof(facing));
|
if (strcmp(sc035gs->module_facing, "back") == 0)
|
facing[0] = 'b';
|
else
|
facing[0] = 'f';
|
|
snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
|
sc035gs->module_index, facing,
|
SC035GS_NAME, dev_name(sd->dev));
|
ret = v4l2_async_register_subdev_sensor_common(sd);
|
if (ret) {
|
dev_err(dev, "v4l2 async register subdev failed\n");
|
goto err_clean_entity;
|
}
|
|
pm_runtime_set_active(dev);
|
pm_runtime_enable(dev);
|
pm_runtime_idle(dev);
|
|
return 0;
|
|
err_clean_entity:
|
#if defined(CONFIG_MEDIA_CONTROLLER)
|
media_entity_cleanup(&sd->entity);
|
#endif
|
err_power_off:
|
__sc035gs_power_off(sc035gs);
|
err_free_handler:
|
v4l2_ctrl_handler_free(&sc035gs->ctrl_handler);
|
err_destroy_mutex:
|
mutex_destroy(&sc035gs->mutex);
|
|
return ret;
|
}
|
|
static int sc035gs_remove(struct i2c_client *client)
|
{
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
struct sc035gs *sc035gs = to_sc035gs(sd);
|
|
v4l2_async_unregister_subdev(sd);
|
#if defined(CONFIG_MEDIA_CONTROLLER)
|
media_entity_cleanup(&sd->entity);
|
#endif
|
v4l2_ctrl_handler_free(&sc035gs->ctrl_handler);
|
mutex_destroy(&sc035gs->mutex);
|
|
pm_runtime_disable(&client->dev);
|
if (!pm_runtime_status_suspended(&client->dev))
|
__sc035gs_power_off(sc035gs);
|
pm_runtime_set_suspended(&client->dev);
|
|
return 0;
|
}
|
|
#if IS_ENABLED(CONFIG_OF)
|
static const struct of_device_id sc035gs_of_match[] = {
|
{ .compatible = "smartsens,sc035gs" },
|
{},
|
};
|
MODULE_DEVICE_TABLE(of, sc035gs_of_match);
|
#endif
|
|
static const struct i2c_device_id sc035gs_match_id[] = {
|
{ "smartsens,sc035gs", 0 },
|
{ },
|
};
|
|
static struct i2c_driver sc035gs_i2c_driver = {
|
.driver = {
|
.name = SC035GS_NAME,
|
.pm = &sc035gs_pm_ops,
|
.of_match_table = of_match_ptr(sc035gs_of_match),
|
},
|
.probe = &sc035gs_probe,
|
.remove = &sc035gs_remove,
|
.id_table = sc035gs_match_id,
|
};
|
|
static int __init sensor_mod_init(void)
|
{
|
return i2c_add_driver(&sc035gs_i2c_driver);
|
}
|
|
static void __exit sensor_mod_exit(void)
|
{
|
i2c_del_driver(&sc035gs_i2c_driver);
|
}
|
|
device_initcall_sync(sensor_mod_init);
|
module_exit(sensor_mod_exit);
|
|
MODULE_DESCRIPTION("Smartsens sc035gs sensor driver");
|
MODULE_LICENSE("GPL");
|
