/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen <csq@rock-chips.com>
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*/
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#ifndef _RK628_MIPI_DPHY_H
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#define _RK628_MIPI_DPHY_H
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include "rk628_csi.h"
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#include "rk628_dsi.h"
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#include "rk628.h"
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/* Test Code: 0x44 (HS RX Control of Lane 0) */
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#define HSFREQRANGE(x) UPDATE(x, 6, 1)
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#define HSTX(x) UPDATE(x, 6, 0)
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#define HSZERO(x) UPDATE(x, 5, 0)
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#define HSPOST(x) UPDATE(x, 4, 0)
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static inline void testif_testclk_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTCLK, PHY_TESTCLK);
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udelay(1);
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}
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static inline void testif_testclk_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTCLK, 0);
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udelay(1);
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}
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static inline void testif_testclr_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTCLR, PHY_TESTCLR);
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udelay(1);
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}
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static inline void testif_testclr_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTCLR, 0);
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udelay(1);
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}
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static inline void testif_testen_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTEN, PHY_TESTEN);
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udelay(1);
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}
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static inline void testif_testen_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTEN, 0);
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udelay(1);
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}
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static inline void testif_set_data(struct rk628 *rk628, u8 data)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTDIN_MASK, PHY_TESTDIN(data));
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udelay(1);
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}
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static inline u8 testif_get_data(struct rk628 *rk628)
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{
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u32 data = 0;
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rk628_i2c_read(rk628, GRF_DPHY0_STATUS, &data);
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return data >> PHY_TESTDOUT_SHIFT;
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}
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static void testif_test_code_write(struct rk628 *rk628, u8 test_code)
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{
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testif_testclk_assert(rk628);
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testif_set_data(rk628, test_code);
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testif_testen_assert(rk628);
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testif_testclk_deassert(rk628);
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testif_testen_deassert(rk628);
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}
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static void testif_test_data_write(struct rk628 *rk628, u8 test_data)
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{
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testif_testclk_deassert(rk628);
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testif_set_data(rk628, test_data);
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testif_testclk_assert(rk628);
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}
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static u8 testif_write(struct rk628 *rk628, u8 test_code, u8 test_data)
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{
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u8 monitor_data;
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testif_test_code_write(rk628, test_code);
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testif_test_data_write(rk628, test_data);
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monitor_data = testif_get_data(rk628);
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dev_dbg(rk628->dev, "test_code=0x%02x, ", test_code);
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dev_dbg(rk628->dev, "test_data=0x%02x, ", test_data);
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dev_dbg(rk628->dev, "monitor_data=0x%02x\n", monitor_data);
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return monitor_data;
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}
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static inline u8 testif_read(struct rk628 *rk628, u8 test_code)
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{
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u8 test_data;
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testif_test_code_write(rk628, test_code);
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test_data = testif_get_data(rk628);
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testif_test_data_write(rk628, test_data);
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return test_data;
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}
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static inline void mipi_dphy_enableclk_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, CSITX_DPHY_CTRL, DPHY_ENABLECLK,
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DPHY_ENABLECLK);
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udelay(1);
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}
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static inline void mipi_dphy_enableclk_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, CSITX_DPHY_CTRL, DPHY_ENABLECLK, 0);
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udelay(1);
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}
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static inline void mipi_dphy_shutdownz_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON, CSI_PHYSHUTDOWNZ, 0);
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udelay(1);
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}
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static inline void mipi_dphy_shutdownz_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON, CSI_PHYSHUTDOWNZ,
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CSI_PHYSHUTDOWNZ);
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udelay(1);
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}
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static inline void mipi_dphy_rstz_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON, CSI_PHYRSTZ, 0);
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udelay(1);
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}
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static inline void mipi_dphy_rstz_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON, CSI_PHYRSTZ,
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CSI_PHYRSTZ);
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udelay(1);
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}
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static inline void mipi_dphy_init_hsfreqrange(struct rk628 *rk628, int lane_mbps)
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{
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const struct {
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unsigned long max_lane_mbps;
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u8 hsfreqrange;
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} hsfreqrange_table[] = {
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{ 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
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{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
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{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
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{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
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{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
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{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
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{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
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{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
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{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
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{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
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};
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u8 hsfreqrange;
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unsigned int index;
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for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
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if (lane_mbps <= hsfreqrange_table[index].max_lane_mbps)
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break;
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if (index == ARRAY_SIZE(hsfreqrange_table))
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--index;
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hsfreqrange = hsfreqrange_table[index].hsfreqrange;
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testif_write(rk628, 0x44, HSFREQRANGE(hsfreqrange));
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}
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static void __maybe_unused mipi_dphy_init_hsmanual(struct rk628 *rk628, bool manual)
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{
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if (manual) {
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//config mipi timing when mipi freq is 1250Mbps
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testif_write(rk628, 0x71, HSTX(0x4a) | BIT(7));
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usleep_range(1500, 2000);
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testif_write(rk628, 0x72, HSZERO(0xf) | BIT(6));
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usleep_range(1500, 2000);
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testif_write(rk628, 0x73, HSTX(0x5d) | BIT(7));
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usleep_range(1500, 2000);
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testif_write(rk628, 0x61, HSTX(0x3a) | BIT(7));
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usleep_range(1500, 2000);
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testif_write(rk628, 0x62, HSZERO(0x3a) | BIT(6));
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usleep_range(1500, 2000);
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testif_write(rk628, 0x63, HSTX(0x5a) | BIT(7));
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usleep_range(1500, 2000);
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testif_write(rk628, 0x65, HSPOST(0x1f) | BIT(5));
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} else {
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testif_write(rk628, 0x71, 0);
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usleep_range(1500, 2000);
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testif_write(rk628, 0x72, 0);
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usleep_range(1500, 2000);
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testif_write(rk628, 0x73, 0);
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usleep_range(1500, 2000);
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testif_write(rk628, 0x61, 0);
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usleep_range(1500, 2000);
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testif_write(rk628, 0x62, 0);
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usleep_range(1500, 2000);
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testif_write(rk628, 0x63, 0);
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usleep_range(1500, 2000);
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testif_write(rk628, 0x65, 0);
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}
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}
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static inline int mipi_dphy_reset(struct rk628 *rk628)
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{
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u32 val, mask;
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mipi_dphy_enableclk_deassert(rk628);
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mipi_dphy_shutdownz_assert(rk628);
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mipi_dphy_rstz_assert(rk628);
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testif_testclr_assert(rk628);
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/* Set all REQUEST inputs to zero */
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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FORCETXSTOPMODE_MASK | FORCERXMODE_MASK,
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FORCETXSTOPMODE(0) | FORCERXMODE(0));
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udelay(1);
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testif_testclr_deassert(rk628);
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mipi_dphy_enableclk_assert(rk628);
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mipi_dphy_shutdownz_deassert(rk628);
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mipi_dphy_rstz_deassert(rk628);
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usleep_range(1500, 2000);
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mask = STOPSTATE_CLK | STOPSTATE_LANE0;
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rk628_i2c_read(rk628, CSITX_CSITX_STATUS1, &val);
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if ((val & mask) != mask) {
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dev_err(rk628->dev, "lane module is not in stop state\n");
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return -1;
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}
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return 0;
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}
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#endif
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