// SPDX-License-Identifier: GPL-2.0
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/*
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* Maxim Quad GMSL Deserializer Test Pattern Driver
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*
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* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
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*
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* Author: Cai Wenzhong <cwz@rock-chips.com>
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*
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*/
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#include "maxim4c_api.h"
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#define PATTERN_WIDTH 1920
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#define PATTERN_HEIGHT 1080
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/* pattern generator: 0 or 1 */
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enum {
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PATTERN_GENERATOR_0 = 0,
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PATTERN_GENERATOR_1,
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};
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/* pattern mode: checkerboard or gradient */
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enum {
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PATTERN_CHECKERBOARD = 0,
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PATTERN_GRADIENT,
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};
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/* pattern pclk: 25M or 75M 0r 150M or 375M */
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enum {
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PATTERN_PCLK_25M = 0,
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PATTERN_PCLK_75M,
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PATTERN_PCLK_150M,
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PATTERN_PCLK_375M,
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};
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static const struct maxim4c_mode maxim4c_pattern_mode = {
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.width = PATTERN_WIDTH,
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.height = PATTERN_HEIGHT,
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.max_fps = {
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.numerator = 10000,
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.denominator = 300000,
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},
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.link_freq_idx = 15,
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.bus_fmt = MEDIA_BUS_FMT_RGB888_1X24,
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.bpp = 24,
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.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
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};
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/* VPG0 or VPG1 register */
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#define VPGx_REG(x, reg) ((reg) + 0x30 * (x))
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int maxim4c_pattern_enable(maxim4c_t *maxim4c, bool enable)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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struct maxim4c_pattern *pattern = &maxim4c->pattern;
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u32 vpgx;
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u32 pattern_mode;
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u8 reg_mask = 0, reg_val = 0;
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int ret = 0;
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dev_info(dev, "video pattern: enable = %d\n", enable);
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vpgx = pattern->pattern_generator;
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pattern_mode = pattern->pattern_mode;
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reg_mask = BIT(5) | BIT(4);
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if (pattern_mode == PATTERN_CHECKERBOARD) {
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/* Generate checkerboard pattern. */
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reg_val = enable ? BIT(4) : 0;
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} else {
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/* Generate gradient pattern. */
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reg_val = enable ? BIT(5) : 0;
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}
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ret = maxim4c_i2c_update_byte(client,
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VPGx_REG(vpgx, 0x1051), MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_val);
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return ret;
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}
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EXPORT_SYMBOL(maxim4c_pattern_enable);
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static int maxim4c_pattern_previnit(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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int ret = 0;
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// All links disable at beginning.
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ret = maxim4c_i2c_write_byte(client,
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0x0006, MAXIM4C_I2C_REG_ADDR_16BITS,
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0xF0);
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if (ret)
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return ret;
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// video pipe disable.
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ret = maxim4c_i2c_write_byte(client,
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0x00F4, MAXIM4C_I2C_REG_ADDR_16BITS,
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0x00);
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if (ret)
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return ret;
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// MIPI CSI output disable.
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ret = maxim4c_i2c_write_byte(client,
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0x040B, MAXIM4C_I2C_REG_ADDR_16BITS,
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0x00);
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if (ret)
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return ret;
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// MIPI TXPHY standby
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ret = maxim4c_i2c_update_byte(client,
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0x08A2, MAXIM4C_I2C_REG_ADDR_16BITS,
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0xF0, 0x00);
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if (ret)
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return ret;
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return 0;
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}
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static int maxim4c_pattern_config(maxim4c_t *maxim4c)
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{
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const u32 h_active = PATTERN_WIDTH;
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const u32 h_fp = 88;
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const u32 h_sw = 44;
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const u32 h_bp = 148;
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const u32 h_tot = h_active + h_fp + h_sw + h_bp;
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const u32 v_active = PATTERN_HEIGHT;
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const u32 v_fp = 4;
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const u32 v_sw = 5;
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const u32 v_bp = 36;
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const u32 v_tot = v_active + v_fp + v_sw + v_bp;
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struct i2c_client *client = maxim4c->client;
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struct maxim4c_pattern *pattern = &maxim4c->pattern;
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u32 vpgx;
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u32 pattern_mode;
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u32 pattern_pclk;
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u16 reg_addr = 0;
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u8 reg_mask = 0, reg_val = 0;
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int ret = 0, i = 0;
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vpgx = pattern->pattern_generator;
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pattern_mode = pattern->pattern_mode;
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pattern_pclk = pattern->pattern_pclk;
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// PATGEN_MODE = 0, Pattern generator disabled
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// use video from the serializer input
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ret |= maxim4c_i2c_update_byte(client,
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VPGx_REG(vpgx, 0x1051), MAXIM4C_I2C_REG_ADDR_16BITS,
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BIT(5) | BIT(4), 0x00);
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/* Pattern PCLK:
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* 0b00 - 25MHz
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* 0b01 - 75MHz
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* 0b1x - (PATGEN_CLK_SRC: 0 - 150MHz, 1 - 375MHz).
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*/
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pattern_pclk = (pattern_pclk & 0x03);
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ret |= maxim4c_i2c_write_byte(client,
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0x0009, MAXIM4C_I2C_REG_ADDR_16BITS,
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pattern_pclk);
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if (pattern_pclk >= PATTERN_PCLK_150M) {
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reg_mask = BIT(7);
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if (pattern_pclk == PATTERN_PCLK_375M)
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reg_val = BIT(7);
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else
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reg_val = 0;
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if (vpgx == PATTERN_GENERATOR_0) {
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for (i = 0; i < 4; i++) {
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reg_addr = 0x01DC + i * 0x20;
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ret |= maxim4c_i2c_update_byte(client,
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reg_addr, MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_val);
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}
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} else {
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for (i = 0; i < 4; i++) {
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reg_addr = 0x025C + i * 0x20;
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ret |= maxim4c_i2c_update_byte(client,
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reg_addr, MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_val);
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}
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}
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}
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/* Configure Video Timing Generator for 1920x1080 @ 30 fps. */
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// VS_DLY = 0
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1052), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_24BITS, 0x000000);
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// VS_HIGH = Vsw * Htot
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1055), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_24BITS, v_sw * h_tot);
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// VS_LOW = (Vactive + Vfp + Vbp) * Htot
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1058), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_24BITS, (v_active + v_fp + v_bp) * h_tot);
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// V2H = VS_DLY
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x105b), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_24BITS, 0x000000);
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// HS_HIGH = Hsw
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x105e), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_16BITS, h_sw);
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// HS_LOW = Hactive + Hfp + Hbp
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1060), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_16BITS, h_active + h_fp + h_bp);
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// HS_CNT = Vtot
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1062), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_16BITS, v_tot);
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// V2D = VS_DLY + Htot * (Vsw + Vbp) + (Hsw + Hbp)
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1064), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_24BITS, h_tot * (v_sw + v_bp) + (h_sw + h_bp));
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// DE_HIGH = Hactive
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1067), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_16BITS, h_active);
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// DE_LOW = Hfp + Hsw + Hbp
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1069), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_16BITS, h_fp + h_sw + h_bp);
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// DE_CNT = Vactive
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x106b), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_16BITS, v_active);
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/* Generate VS, HS and DE in free-running mode, Invert HS and VS. */
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ret |= maxim4c_i2c_write_byte(client,
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VPGx_REG(vpgx, 0x1050), MAXIM4C_I2C_REG_ADDR_16BITS,
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0xfb);
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/* Configure Video Pattern Generator. */
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if (pattern_mode == PATTERN_CHECKERBOARD) {
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/* Set checkerboard pattern size. */
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1074), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_24BITS, 0x3c3c3c);
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/* Set checkerboard pattern colors. */
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x106e), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_24BITS, 0xfecc00);
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ret |= maxim4c_i2c_write_reg(client,
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VPGx_REG(vpgx, 0x1071), MAXIM4C_I2C_REG_ADDR_16BITS,
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MAXIM4C_I2C_REG_VALUE_24BITS, 0x006aa7);
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} else {
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/* Set gradient increment. */
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ret |= maxim4c_i2c_write_byte(client,
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VPGx_REG(vpgx, 0x106d), MAXIM4C_I2C_REG_ADDR_16BITS,
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0x10);
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}
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return ret;
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}
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int maxim4c_pattern_support_mode_init(maxim4c_t *maxim4c)
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{
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struct device *dev = &maxim4c->client->dev;
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struct maxim4c_mode *supported_mode = NULL;
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dev_info(dev, "=== maxim4c pattern support mode init ===\n");
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maxim4c->cfg_modes_num = 1;
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maxim4c->cur_mode = &maxim4c->supported_mode;
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supported_mode = &maxim4c->supported_mode;
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// init using def mode
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memcpy(supported_mode, &maxim4c_pattern_mode, sizeof(struct maxim4c_mode));
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return 0;
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}
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EXPORT_SYMBOL(maxim4c_pattern_support_mode_init);
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int maxim4c_pattern_data_init(maxim4c_t *maxim4c)
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{
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struct device *dev = &maxim4c->client->dev;
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struct device_node *node = NULL;
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struct maxim4c_mode *supported_mode = NULL;
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struct maxim4c_pattern *pattern = NULL;
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maxim4c_mipi_txphy_t *mipi_txphy = &maxim4c->mipi_txphy;
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int ret = 0;
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// maxim serdes local
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node = of_get_child_by_name(dev->of_node, "serdes-local-device");
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if (IS_ERR_OR_NULL(node)) {
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dev_err(dev, "%pOF has no child node: serdes-local-device\n",
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dev->of_node);
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return -ENODEV;
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}
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if (!of_device_is_available(node)) {
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dev_info(dev, "%pOF is disabled\n", node);
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of_node_put(node);
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return -ENODEV;
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}
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maxim4c_mipi_txphy_data_init(maxim4c);
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/* mipi txphy parse dt */
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ret = maxim4c_mipi_txphy_parse_dt(maxim4c, node);
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if (ret) {
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dev_err(dev, "%s: txphy parse dt error\n", __func__);
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return ret;
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}
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// pattern need enable force_clock_out_en
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dev_info(dev, "Pattern mode force_clock_out_en default enable\n");
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mipi_txphy->force_clock_out_en = 1;
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// pattern generator and mode init
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pattern = &maxim4c->pattern;
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pattern->pattern_generator = PATTERN_GENERATOR_0;
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pattern->pattern_mode = PATTERN_CHECKERBOARD;
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pattern->pattern_pclk = PATTERN_PCLK_75M;
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supported_mode = &maxim4c->supported_mode;
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switch (pattern->pattern_pclk) {
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case PATTERN_PCLK_25M:
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supported_mode->max_fps.denominator = 100000;
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break;
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case PATTERN_PCLK_75M:
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supported_mode->max_fps.denominator = 300000;
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break;
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case PATTERN_PCLK_150M:
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supported_mode->max_fps.denominator = 600000;
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if (supported_mode->link_freq_idx < 12)
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dev_warn(dev, "link_freq_idx = %d is too low\n",
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supported_mode->link_freq_idx);
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break;
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case PATTERN_PCLK_375M:
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supported_mode->max_fps.denominator = 1500000;
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if (supported_mode->link_freq_idx < 22)
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dev_warn(dev, "link_freq_idx = %d is too low\n",
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supported_mode->link_freq_idx);
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break;
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}
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dev_info(dev, "video pattern: generator = %d, mode = %d, pclk = %d\n",
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pattern->pattern_generator, pattern->pattern_mode, pattern->pattern_pclk);
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return 0;
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}
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EXPORT_SYMBOL(maxim4c_pattern_data_init);
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int maxim4c_pattern_hw_init(maxim4c_t *maxim4c)
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{
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struct device *dev = &maxim4c->client->dev;
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int ret = 0;
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ret = maxim4c_pattern_previnit(maxim4c);
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if (ret) {
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dev_err(dev, "%s: pattern previnit error\n", __func__);
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return ret;
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}
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ret = maxim4c_mipi_txphy_hw_init(maxim4c);
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if (ret) {
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dev_err(dev, "%s: txphy hw init error\n", __func__);
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return ret;
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}
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ret = maxim4c_pattern_config(maxim4c);
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if (ret) {
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dev_err(dev, "%s: pattern config error\n", __func__);
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL(maxim4c_pattern_hw_init);
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