/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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#ifndef __MAXIM4C_MIPI_TXPHY_H__
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#define __MAXIM4C_MIPI_TXPHY_H__
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/* MIPI TXPHY ID: 0 ~ 3 */
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enum {
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MAXIM4C_TXPHY_ID_A = 0,
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MAXIM4C_TXPHY_ID_B,
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MAXIM4C_TXPHY_ID_C,
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MAXIM4C_TXPHY_ID_D,
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MAXIM4C_TXPHY_ID_MAX,
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};
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/* MIPI TXPHY Bit Mask: bit0 ~ bit3 */
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#define MAXIM4C_TXPHY_MASK_A BIT(MAXIM4C_TXPHY_ID_A)
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#define MAXIM4C_TXPHY_MASK_B BIT(MAXIM4C_TXPHY_ID_B)
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#define MAXIM4C_TXPHY_MASK_C BIT(MAXIM4C_TXPHY_ID_C)
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#define MAXIM4C_TXPHY_MASK_D BIT(MAXIM4C_TXPHY_ID_D)
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#define MAXIM4C_TXPHY_MASK_ALL GENMASK(MAXIM4C_TXPHY_ID_D, MAXIM4C_TXPHY_ID_A)
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/* MIPI TXPHY Type */
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enum {
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MAXIM4C_TXPHY_TYPE_DPHY = 0,
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MAXIM4C_TXPHY_TYPE_CPHY,
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};
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/* MIPI TXPHY Mode */
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enum {
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MAXIM4C_TXPHY_MODE_2X4LANES = 0, /* PortA: 1x4Lanes, PortB: 1x4Lanes */
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MAXIM4C_TXPHY_MODE_4X2LANES, /* PortA: 2x2Lanes, PortB: 2x2Lanes */
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MAXIM4C_TXPHY_MODE_1X4LANES_2X2LANES, /* PortA: 1x4Lanes, PortB: 2x2Lanes */
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MAXIM4C_TXPHY_MODE_2X2LANES_1X4LANES, /* PortA: 2x2Lanes, PortB: 1x4Lanes */
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};
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/* MIPI TXPHY DPLL */
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enum {
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MAXIM4C_TXPHY_DPLL_PREDEF = 0,
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MAXIM4C_TXPHY_DPLL_FINE_TUNING,
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};
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struct maxim4c_txphy_cfg {
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u8 phy_enable;
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u8 phy_type;
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u8 auto_deskew;
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u8 data_lane_num;
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u8 data_lane_map;
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u8 vc_ext_en;
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u8 clock_master;
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u8 clock_mode;
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};
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typedef struct maxim4c_mipi_txphy {
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u8 phy_mode; /* mipi txphy mode */
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u8 force_clock_out_en; /* Force all MIPI clocks running */
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u8 force_clk0_en; /* DPHY0 enabled as clock */
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u8 force_clk3_en; /* DPHY3 enabled as clock */
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struct maxim4c_txphy_cfg phy_cfg[MAXIM4C_TXPHY_ID_MAX];
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} maxim4c_mipi_txphy_t;
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#endif /* __MAXIM4C_MIPI_TXPHY_H__ */
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