// SPDX-License-Identifier: GPL-2.0
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/*
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* Maxim Quad GMSL Deserializer Link driver
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*
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* Copyright (C) 2023 Rockchip Electronics Co., Ltd.
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*
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* Author: Cai Wenzhong <cwz@rock-chips.com>
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*
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*/
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#include <linux/delay.h>
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#include "maxim4c_api.h"
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static int maxim4c_link_enable_vdd_ldo1(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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int ret = 0;
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/* IF VDD = 1.2V: Enable REG_ENABLE and REG_MNL
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* CTRL0: Enable REG_ENABLE
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* CTRL2: Enable REG_MNL
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*/
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ret |= maxim4c_i2c_update_byte(client,
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0x0017, MAXIM4C_I2C_REG_ADDR_16BITS, BIT(2), BIT(2));
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ret |= maxim4c_i2c_update_byte(client,
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0x0019, MAXIM4C_I2C_REG_ADDR_16BITS, BIT(4), BIT(4));
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return ret;
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}
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static int maxim4c_link_enable_vdd_ldo2(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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int ret = 0;
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ret |= maxim4c_i2c_write_byte(client,
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0x06C2, MAXIM4C_I2C_REG_ADDR_16BITS,
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0x10);
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// delay 10ms
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msleep(10);
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return ret;
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}
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static int maxim4c_link_set_rate(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
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struct maxim4c_link_cfg *link_cfg = NULL;
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u8 link_rate = 0;
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int ret = 0;
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/* Link A/B rate setting */
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link_rate = 0; /* default Transmitter Rate is 187.5Mbps */
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link_cfg = &gmsl_link->link_cfg[MAXIM4C_LINK_ID_A];
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if (link_cfg->link_enable) {
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/* Link A: Receiver Rate */
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if (link_cfg->link_rx_rate == MAXIM4C_LINK_RX_RATE_3GBPS)
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link_rate |= (0x1 << 0);
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else
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link_rate |= (0x2 << 0);
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}
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link_cfg = &gmsl_link->link_cfg[MAXIM4C_LINK_ID_B];
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if (link_cfg->link_enable) {
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/* Link B: Receiver Rate */
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if (link_cfg->link_rx_rate == MAXIM4C_LINK_RX_RATE_3GBPS)
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link_rate |= (0x1 << 4);
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else
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link_rate |= (0x2 << 4);
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}
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if (link_rate != 0) {
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ret |= maxim4c_i2c_write_byte(client,
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0x0010, MAXIM4C_I2C_REG_ADDR_16BITS,
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link_rate);
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}
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/* Link C/D rate setting */
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link_rate = 0;
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link_cfg = &gmsl_link->link_cfg[MAXIM4C_LINK_ID_C];
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if (link_cfg->link_enable) {
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/* Link C: Receiver Rate */
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if (link_cfg->link_rx_rate == MAXIM4C_LINK_RX_RATE_3GBPS)
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link_rate |= (0x1 << 0);
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else
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link_rate |= (0x2 << 0);
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}
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link_cfg = &gmsl_link->link_cfg[MAXIM4C_LINK_ID_D];
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if (link_cfg->link_enable) {
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/* Link D: Receiver Rate */
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if (link_cfg->link_rx_rate == MAXIM4C_LINK_RX_RATE_3GBPS)
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link_rate |= (0x1 << 4);
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else
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link_rate |= (0x2 << 4);
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}
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if (link_rate != 0) {
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ret |= maxim4c_i2c_write_byte(client,
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0x0011, MAXIM4C_I2C_REG_ADDR_16BITS,
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link_rate);
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}
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return ret;
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}
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static int maxim4c_link_run_init_seq(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
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struct maxim4c_link_cfg *link_cfg = NULL;
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struct maxim4c_i2c_init_seq *init_seq = NULL;
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int link_idx = 0;
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int ret = 0;
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// link init sequence
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
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link_cfg = &gmsl_link->link_cfg[link_idx];
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init_seq = &link_cfg->link_init_seq;
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ret = maxim4c_i2c_run_init_seq(client, init_seq);
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if (ret) {
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dev_err(dev, "link id = %d init sequence error\n", link_idx);
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return ret;
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}
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}
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return 0;
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}
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static int maxim4c_link_status_init(maxim4c_t *maxim4c)
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{
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struct i2c_client *client = maxim4c->client;
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maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
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struct maxim4c_link_cfg *link_cfg = NULL;
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u8 link_type = 0, link_enable = 0;
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u8 reg_mask = 0, reg_value = 0;
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u16 reg_addr = 0;
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int ret = 0, link_idx = 0;
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gmsl_link->link_enable_mask = 0x00;
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gmsl_link->link_type_mask = 0x0F;
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gmsl_link->link_locked_mask = 0;
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link_type = 0xF0; /* default GMSL2 */
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link_enable = 0; /* default disable */
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
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link_cfg = &gmsl_link->link_cfg[link_idx];
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if (link_cfg->link_enable) {
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gmsl_link->link_enable_mask |= BIT(link_idx);
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if (link_cfg->link_type == MAXIM4C_GMSL1) {
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gmsl_link->link_type_mask &= ~BIT(link_idx);
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link_type &= ~BIT(4 + link_idx);
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}
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}
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}
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ret = maxim4c_i2c_write_byte(client,
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0x0006, MAXIM4C_I2C_REG_ADDR_16BITS,
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link_type | link_enable);
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reg_mask = BIT(1) | BIT(0);
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reg_value = 0;
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
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reg_addr = 0x0B04 + 0x100 * link_idx;
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ret |= maxim4c_i2c_update_byte(client,
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reg_addr, MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_value);
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}
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if (gmsl_link->i2c_ctrl_port == MAXIM4C_I2C_PORT2) {
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reg_mask = 0x0F;
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reg_value = 0x0F;
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ret |= maxim4c_i2c_update_byte(client,
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0x000E, MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_value);
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}
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reg_mask = 0xFF;
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reg_value = 0xFF;
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ret |= maxim4c_i2c_update_byte(client,
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0x0003, MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_value);
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return ret;
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}
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u8 maxim4c_link_get_lock_state(maxim4c_t *maxim4c, u8 link_mask)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
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u8 link_type = 0, link_lock = 0, lock_state = 0;
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dev_dbg(dev, "%s, link_mask = 0x%x\n", __func__, link_mask);
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// Link A
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if (link_mask & MAXIM4C_LINK_MASK_A) {
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link_type = gmsl_link->link_cfg[MAXIM4C_LINK_ID_A].link_type;
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if (link_type == MAXIM4C_GMSL2) {
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// GMSL2 Link A
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maxim4c_i2c_read_byte(client,
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0x001A, MAXIM4C_I2C_REG_ADDR_16BITS,
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&link_lock);
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if (link_lock & BIT(3)) {
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lock_state |= MAXIM4C_LINK_MASK_A;
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dev_dbg(dev, "GMSL2 Link A locked\n");
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}
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} else {
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// GMSL1 Link A
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maxim4c_i2c_read_byte(client,
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0x0BCB, MAXIM4C_I2C_REG_ADDR_16BITS,
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&link_lock);
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if (link_lock & BIT(0)) {
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lock_state |= MAXIM4C_LINK_MASK_A;
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dev_dbg(dev, "GMSL1 Link A locked\n");
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}
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}
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// record link lock
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if (lock_state & MAXIM4C_LINK_MASK_A)
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gmsl_link->link_locked_mask |= MAXIM4C_LINK_MASK_A;
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else
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gmsl_link->link_locked_mask &= ~MAXIM4C_LINK_MASK_A;
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}
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// Link B
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if (link_mask & MAXIM4C_LINK_MASK_B) {
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link_type = gmsl_link->link_cfg[MAXIM4C_LINK_ID_B].link_type;
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if (link_type == MAXIM4C_GMSL2) {
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// GMSL2 Link B
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maxim4c_i2c_read_byte(client,
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0x000A, MAXIM4C_I2C_REG_ADDR_16BITS,
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&link_lock);
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if (link_lock & BIT(3)) {
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lock_state |= MAXIM4C_LINK_MASK_B;
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dev_dbg(dev, "GMSL2 Link B locked\n");
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}
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} else {
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// GMSL1 Link B
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maxim4c_i2c_read_byte(client,
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0x0CCB, MAXIM4C_I2C_REG_ADDR_16BITS,
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&link_lock);
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if (link_lock & BIT(0)) {
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lock_state |= MAXIM4C_LINK_MASK_B;
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dev_dbg(dev, "GMSL1 Link B locked\n");
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}
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}
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// record link lock
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if (lock_state & MAXIM4C_LINK_MASK_B)
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gmsl_link->link_locked_mask |= MAXIM4C_LINK_MASK_B;
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else
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gmsl_link->link_locked_mask &= ~MAXIM4C_LINK_MASK_B;
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}
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// Link C
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if (link_mask & MAXIM4C_LINK_MASK_C) {
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link_type = gmsl_link->link_cfg[MAXIM4C_LINK_ID_C].link_type;
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if (link_type == MAXIM4C_GMSL2) {
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// GMSL2 Link C
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maxim4c_i2c_read_byte(client,
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0x000B, MAXIM4C_I2C_REG_ADDR_16BITS,
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&link_lock);
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if (link_lock & BIT(3)) {
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lock_state |= MAXIM4C_LINK_MASK_C;
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dev_dbg(dev, "GMSL2 Link C locked\n");
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}
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} else {
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// GMSL1 Link C
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maxim4c_i2c_read_byte(client,
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0x0DCB, MAXIM4C_I2C_REG_ADDR_16BITS,
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&link_lock);
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if (link_lock & BIT(0)) {
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lock_state |= MAXIM4C_LINK_MASK_C;
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dev_dbg(dev, "GMSL1 Link C locked\n");
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}
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}
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// record link lock
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if (lock_state & MAXIM4C_LINK_MASK_C)
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gmsl_link->link_locked_mask |= MAXIM4C_LINK_MASK_C;
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else
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gmsl_link->link_locked_mask &= ~MAXIM4C_LINK_MASK_C;
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}
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// Link D
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if (link_mask & MAXIM4C_LINK_MASK_D) {
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link_type = gmsl_link->link_cfg[MAXIM4C_LINK_ID_D].link_type;
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if (link_type == MAXIM4C_GMSL2) {
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// GMSL2 Link D
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maxim4c_i2c_read_byte(client,
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0x000C, MAXIM4C_I2C_REG_ADDR_16BITS,
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&link_lock);
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if (link_lock & BIT(3)) {
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lock_state |= MAXIM4C_LINK_MASK_D;
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dev_dbg(dev, "GMSL2 Link D locked\n");
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}
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} else {
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// GMSL1 Link D
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maxim4c_i2c_read_byte(client,
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0x0ECB, MAXIM4C_I2C_REG_ADDR_16BITS,
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&link_lock);
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if (link_lock & BIT(0)) {
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lock_state |= MAXIM4C_LINK_MASK_D;
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dev_dbg(dev, "GMSL1 Link D locked\n");
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}
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}
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// record link lock
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if (lock_state & MAXIM4C_LINK_MASK_D)
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gmsl_link->link_locked_mask |= MAXIM4C_LINK_MASK_D;
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else
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gmsl_link->link_locked_mask &= ~MAXIM4C_LINK_MASK_D;
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}
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return lock_state;
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}
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EXPORT_SYMBOL(maxim4c_link_get_lock_state);
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int maxim4c_link_oneshot_reset(struct maxim4c *maxim4c, u8 link_mask)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
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struct maxim4c_link_cfg *link_cfg = NULL;
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u8 oneshot_reset = 0;
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int ret = 0, link_idx = 0;
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dev_dbg(dev, "%s, link_mask = 0x%x\n", __func__, link_mask);
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oneshot_reset = 0;
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
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link_cfg = &gmsl_link->link_cfg[link_idx];
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if (link_cfg->link_enable && (link_mask & BIT(link_idx)))
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oneshot_reset |= BIT(link_idx);
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}
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if (oneshot_reset != 0) {
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// One-Shot Reset
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ret = maxim4c_i2c_write_byte(client,
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0x0018, MAXIM4C_I2C_REG_ADDR_16BITS,
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oneshot_reset);
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}
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return ret;
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}
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EXPORT_SYMBOL(maxim4c_link_oneshot_reset);
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int maxim4c_link_mask_enable(struct maxim4c *maxim4c, u8 link_mask, bool enable)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
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struct maxim4c_link_cfg *link_cfg = NULL;
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u8 reg_mask = 0, reg_value = 0;
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int ret = 0, link_idx = 0;
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dev_dbg(dev, "%s, link_mask = 0x%x, enable = %d\n",
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__func__, link_mask, enable);
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reg_mask = 0;
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
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link_cfg = &gmsl_link->link_cfg[link_idx];
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if (link_cfg->link_enable && (link_mask & BIT(link_idx)))
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reg_mask |= BIT(link_idx);
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}
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if (reg_mask != 0) {
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reg_value = enable ? reg_mask : 0;
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ret = maxim4c_i2c_update_byte(client,
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0x0006, MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_value);
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}
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return ret;
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}
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EXPORT_SYMBOL(maxim4c_link_mask_enable);
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int maxim4c_link_wait_linklock(struct maxim4c *maxim4c, u8 link_mask)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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u8 lock_state = 0, link_bit_mask = 0;
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int loop_idx = 0, time_ms = 0, link_idx = 0;
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time_ms = 50;
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msleep(time_ms);
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for (loop_idx = 0; loop_idx < 20; loop_idx++) {
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if (loop_idx != 0) {
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msleep(10);
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time_ms += 10;
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}
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
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link_bit_mask = BIT(link_idx);
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if ((link_mask & link_bit_mask)
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&& ((lock_state & link_bit_mask) == 0)) {
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if (maxim4c_link_get_lock_state(maxim4c, link_bit_mask)) {
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lock_state |= link_bit_mask;
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dev_info(dev, "Link %c locked time: %d ms\n",
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'A' + link_idx, time_ms);
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}
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}
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}
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if ((lock_state & link_mask) == link_mask) {
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dev_info(dev, "All Links are locked: 0x%x, time_ms = %d\n",
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lock_state, time_ms);
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maxim4c->link_lock_state = lock_state;
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return 0;
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}
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}
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if ((lock_state & link_mask) != 0) {
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dev_info(dev, "Partial links are locked: 0x%x, time_ms = %d\n",
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lock_state, time_ms);
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maxim4c->link_lock_state = lock_state;
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return 0;
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} else {
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dev_err(dev, "Failed to detect remote link, time_ms = %d!\n", time_ms);
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maxim4c->link_lock_state = 0;
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return -ENODEV;
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}
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}
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EXPORT_SYMBOL(maxim4c_link_wait_linklock);
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int maxim4c_link_select_remote_enable(struct maxim4c *maxim4c, u8 link_mask)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
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u8 link_enable = 0, link_reset = 0, link_bit_mask = 0;
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int ret = 0, link_idx = 0;
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dev_dbg(dev, "%s, link_mask = 0x%x\n", __func__, link_mask);
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ret = 0;
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link_enable = 0;
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link_reset = 0;
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
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link_bit_mask = BIT(link_idx);
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if (link_mask & link_bit_mask) {
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if (gmsl_link->link_cfg[link_idx].link_enable) {
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link_enable |= BIT(link_idx);
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link_reset |= BIT(link_idx);
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} else {
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link_mask &= ~link_bit_mask;
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}
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}
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}
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if (link_mask != 0) {
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// One-Shot Reset
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ret |= maxim4c_i2c_write_byte(client,
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0x0018, MAXIM4C_I2C_REG_ADDR_16BITS,
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link_reset);
|
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// Link Enable
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ret |= maxim4c_i2c_update_byte(client,
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0x0006, MAXIM4C_I2C_REG_ADDR_16BITS,
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link_enable, link_enable);
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ret |= maxim4c_link_wait_linklock(maxim4c, link_mask);
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}
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return ret;
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}
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EXPORT_SYMBOL(maxim4c_link_select_remote_enable);
|
|
int maxim4c_link_select_remote_control(struct maxim4c *maxim4c, u8 link_mask)
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{
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struct i2c_client *client = maxim4c->client;
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struct device *dev = &client->dev;
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maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
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struct maxim4c_link_cfg *link_cfg = NULL;
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u8 link_enable = 0, link_type = 0;
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u8 reg_mask = 0, reg_value = 0;
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u16 reg_addr = 0;
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int link_idx = 0, ret = 0;
|
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dev_dbg(dev, "%s, link mask = 0x%x\n", __func__, link_mask);
|
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// GMSL1 Link forward control channel
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
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link_cfg = &gmsl_link->link_cfg[link_idx];
|
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link_enable = link_cfg->link_enable;
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link_type = link_cfg->link_type;
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if (link_enable && (link_type == MAXIM4C_GMSL1)) {
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reg_mask = BIT(1) | BIT(0);
|
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if (link_mask & BIT(link_idx))
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// GMSL1: Enable forward control channel transmitter
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reg_value = BIT(1) | BIT(0);
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else
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// GMSL1: Disable forward control channel transmitter
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reg_value = 0;
|
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reg_addr = 0x0B04 + 0x100 * link_idx;
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ret |= maxim4c_i2c_update_byte(client,
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reg_addr, MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_value);
|
|
link_mask &= ~BIT(link_idx);
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}
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}
|
|
// GMSL2 Link
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if (gmsl_link->i2c_ctrl_port == MAXIM4C_I2C_PORT2) {
|
reg_mask = 0x0F;
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reg_value = ~link_mask;
|
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ret |= maxim4c_i2c_update_byte(client,
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0x000E, MAXIM4C_I2C_REG_ADDR_16BITS,
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reg_mask, reg_value);
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} else if (gmsl_link->i2c_ctrl_port == MAXIM4C_I2C_PORT1) {
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reg_mask = 0xFF;
|
reg_value = 0;
|
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for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
|
if (link_mask & BIT(link_idx))
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reg_value |= BIT(1 + 2 * link_idx);
|
}
|
reg_value = ~reg_value;
|
|
ret |= maxim4c_i2c_update_byte(client,
|
0x0003, MAXIM4C_I2C_REG_ADDR_16BITS,
|
reg_mask, reg_value);
|
} else {
|
reg_mask = 0xFF;
|
reg_value = 0;
|
|
for (link_idx = 0; link_idx < MAXIM4C_LINK_ID_MAX; link_idx++) {
|
if (link_mask & BIT(link_idx))
|
reg_value |= BIT(0 + 2 * link_idx);
|
}
|
reg_value = ~reg_value;
|
|
ret |= maxim4c_i2c_update_byte(client,
|
0x0003, MAXIM4C_I2C_REG_ADDR_16BITS,
|
reg_mask, reg_value);
|
}
|
|
return ret;
|
}
|
EXPORT_SYMBOL(maxim4c_link_select_remote_control);
|
|
static int maxim4c_gmsl_link_config_parse_dt(struct device *dev,
|
maxim4c_gmsl_link_t *gmsl_link,
|
struct device_node *parent_node)
|
{
|
struct device_node *node = NULL;
|
struct device_node *init_seq_node = NULL;
|
struct maxim4c_i2c_init_seq *init_seq = NULL;
|
struct maxim4c_link_cfg *link_cfg = NULL;
|
const char *link_cfg_name = "gmsl-link-config";
|
u32 value = 0;
|
u32 sub_idx = 0, link_id = 0;
|
int ret = 0;
|
|
node = NULL;
|
sub_idx = 0;
|
while ((node = of_get_next_child(parent_node, node))) {
|
if (!strncasecmp(node->name,
|
link_cfg_name,
|
strlen(link_cfg_name))) {
|
if (sub_idx >= MAXIM4C_LINK_ID_MAX) {
|
dev_err(dev, "%pOF: Too many matching %s node\n",
|
parent_node, link_cfg_name);
|
|
of_node_put(node);
|
break;
|
}
|
|
if (!of_device_is_available(node)) {
|
dev_info(dev, "%pOF is disabled\n", node);
|
|
sub_idx++;
|
|
continue;
|
}
|
|
/* GMSL LINK: link id */
|
ret = of_property_read_u32(node, "link-id", &link_id);
|
if (ret) {
|
// if link_id is error, parse next node
|
dev_err(dev, "Can not get link-id property!");
|
|
sub_idx++;
|
|
continue;
|
}
|
if (link_id >= MAXIM4C_LINK_ID_MAX) {
|
// if link_id is error, parse next node
|
dev_err(dev, "Error link-id = %d!", link_id);
|
|
sub_idx++;
|
|
continue;
|
}
|
|
link_cfg = &gmsl_link->link_cfg[link_id];
|
|
/* GMSL LINK: link enable */
|
link_cfg->link_enable = 1;
|
|
dev_info(dev, "gmsl link id = %d: link_enable = %d\n",
|
link_id, link_cfg->link_enable);
|
|
/* GMSL LINK: other config */
|
ret = of_property_read_u32(node, "link-type", &value);
|
if (ret == 0) {
|
dev_info(dev, "link-type property: %d", value);
|
link_cfg->link_type = value;
|
}
|
|
ret = of_property_read_u32(node, "link-rx-rate", &value);
|
if (ret == 0) {
|
dev_info(dev, "link-rx-rate property: %d", value);
|
link_cfg->link_rx_rate = value;
|
}
|
|
/* link init sequence */
|
init_seq_node = of_get_child_by_name(node, "link-init-sequence");
|
if (!IS_ERR_OR_NULL(init_seq_node)) {
|
dev_info(dev, "load pipe-init-sequence\n");
|
|
init_seq = &link_cfg->link_init_seq;
|
maxim4c_i2c_load_init_seq(dev,
|
init_seq_node, init_seq);
|
|
of_node_put(init_seq_node);
|
}
|
|
sub_idx++;
|
}
|
}
|
|
return 0;
|
}
|
|
int maxim4c_link_parse_dt(maxim4c_t *maxim4c, struct device_node *of_node)
|
{
|
struct device *dev = &maxim4c->client->dev;
|
struct device_node *node = NULL;
|
maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
|
u32 value = 0;
|
int ret = 0;
|
|
dev_info(dev, "=== maxim4c link parse dt ===\n");
|
|
node = of_get_child_by_name(of_node, "gmsl-links");
|
if (IS_ERR_OR_NULL(node)) {
|
dev_err(dev, "%pOF has no child node: gmsl-links\n",
|
of_node);
|
return -ENODEV;
|
}
|
|
if (!of_device_is_available(node)) {
|
dev_info(dev, "%pOF is disabled\n", node);
|
of_node_put(node);
|
return -ENODEV;
|
}
|
|
/* vdd 1.2v ldo1 enable */
|
ret = of_property_read_u32(node, "link-vdd-ldo1-en", &value);
|
if (ret == 0) {
|
dev_info(dev, "link-vdd-ldo1-en property: %d\n", value);
|
gmsl_link->link_vdd_ldo1_en = value;
|
}
|
|
/* vdd ldo2 enable */
|
ret = of_property_read_u32(node, "link-vdd-ldo2-en", &value);
|
if (ret == 0) {
|
dev_info(dev, "link-vdd-ldo2-en property: %d\n", value);
|
gmsl_link->link_vdd_ldo2_en = value;
|
}
|
|
ret = maxim4c_gmsl_link_config_parse_dt(dev, gmsl_link, node);
|
|
of_node_put(node);
|
|
return ret;
|
}
|
EXPORT_SYMBOL(maxim4c_link_parse_dt);
|
|
int maxim4c_link_hw_init(maxim4c_t *maxim4c)
|
{
|
struct device *dev = &maxim4c->client->dev;
|
maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
|
int ret = 0;
|
|
// All links disable at beginning.
|
ret = maxim4c_link_status_init(maxim4c);
|
if (ret) {
|
dev_err(dev, "%s: link status error\n", __func__);
|
return ret;
|
}
|
|
if (gmsl_link->link_vdd_ldo1_en)
|
ret |= maxim4c_link_enable_vdd_ldo1(maxim4c);
|
|
if (gmsl_link->link_vdd_ldo2_en)
|
ret |= maxim4c_link_enable_vdd_ldo2(maxim4c);
|
if (ret) {
|
dev_err(dev, "%s: link vdd ldo enable error\n", __func__);
|
return ret;
|
}
|
|
// Link Rate Setting
|
ret = maxim4c_link_set_rate(maxim4c);
|
if (ret) {
|
dev_err(dev, "%s: link set rate error\n", __func__);
|
return ret;
|
}
|
|
// link init sequence
|
ret = maxim4c_link_run_init_seq(maxim4c);
|
if (ret) {
|
dev_err(dev, "%s: link run init seq error\n", __func__);
|
return ret;
|
}
|
|
return 0;
|
}
|
EXPORT_SYMBOL(maxim4c_link_hw_init);
|
|
void maxim4c_link_data_init(maxim4c_t *maxim4c)
|
{
|
maxim4c_gmsl_link_t *gmsl_link = &maxim4c->gmsl_link;
|
struct maxim4c_link_cfg *link_cfg = NULL;
|
int i = 0;
|
|
gmsl_link->link_vdd_ldo1_en = 0;
|
gmsl_link->link_vdd_ldo2_en = 0;
|
gmsl_link->i2c_ctrl_port = MAXIM4C_I2C_PORT0;
|
|
for (i = 0; i < MAXIM4C_LINK_ID_MAX; i++) {
|
link_cfg = &gmsl_link->link_cfg[i];
|
|
link_cfg->link_enable = 0;
|
link_cfg->link_type = MAXIM4C_GMSL2;
|
if (maxim4c->chipid == MAX96722_CHIP_ID)
|
link_cfg->link_rx_rate = MAXIM4C_LINK_RX_RATE_3GBPS;
|
else
|
link_cfg->link_rx_rate = MAXIM4C_LINK_RX_RATE_6GBPS;
|
link_cfg->link_tx_rate = MAXIM4C_LINK_TX_RATE_187_5MPS;
|
link_cfg->link_init_seq.reg_init_seq = NULL;
|
}
|
}
|
EXPORT_SYMBOL(maxim4c_link_data_init);
|
