/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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#ifndef __MAXIM4C_I2C_H__
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#define __MAXIM4C_I2C_H__
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#include <linux/i2c.h>
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/* register address: 8bit or 16bit */
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#define MAXIM4C_I2C_REG_ADDR_08BITS 1
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#define MAXIM4C_I2C_REG_ADDR_16BITS 2
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/* register value: 8bit or 16bit or 24bit */
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#define MAXIM4C_I2C_REG_VALUE_08BITS 1
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#define MAXIM4C_I2C_REG_VALUE_16BITS 2
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#define MAXIM4C_I2C_REG_VALUE_24BITS 3
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/* I2C Device ID */
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enum {
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MAXIM4C_I2C_DES_DEF, /* Deserializer I2C address: Default */
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MAXIM4C_I2C_SER_DEF, /* Serializer I2C address: Default */
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MAXIM4C_I2C_SER_MAP, /* Serializer I2C address: Mapping */
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MAXIM4C_I2C_CAM_DEF, /* Camera I2C address: Default */
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MAXIM4C_I2C_CAM_MAP, /* Camera I2C address: Mapping */
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MAXIM4C_I2C_DEV_MAX,
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};
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/* i2c register array end */
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#define MAXIM4C_REG_NULL 0xFFFF
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struct maxim4c_i2c_regval {
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u16 reg_len;
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u16 reg_addr;
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u32 val_len;
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u32 reg_val;
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u32 val_mask;
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u8 delay;
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};
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/* seq_item_size = reg_len + val_len * 2 + 1 */
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struct maxim4c_i2c_init_seq {
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struct maxim4c_i2c_regval *reg_init_seq;
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u32 reg_seq_size;
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u32 seq_item_size;
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u32 reg_len;
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u32 val_len;
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};
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#endif /* __MAXIM4C_I2C_H__ */
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