// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Zorro Liu <zorro.liu@rock-chips.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/pm_runtime.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "ebc_tcon.h"
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#define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16))
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#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
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#define REG_LOAD_GLOBAL_EN 0x1
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/* ebc register define */
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#define EBC_DSP_START 0x0000 //Frame statrt register
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#define EBC_EPD_CTRL 0x0004 //EPD control register
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#define EBC_DSP_CTRL 0x0008 //Display control register
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#define EBC_DSP_HTIMING0 0x000c //H-Timing setting register0
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#define EBC_DSP_HTIMING1 0x0010 //H-Timing setting register1
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#define EBC_DSP_VTIMING0 0x0014 //V-Timing setting register0
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#define EBC_DSP_VTIMING1 0x0018 //V-Timing setting register1
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#define EBC_DSP_ACT_INFO 0x001c //ACTIVE width/height
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#define EBC_WIN_CTRL 0x0020 //Window ctrl
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#define EBC_WIN_MST0 0x0024 //Current win memory start
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#define EBC_WIN_MST1 0x0028 //Next win memory start
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#define EBC_WIN_VIR 0x002c //Window vir width/height
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#define EBC_WIN_ACT 0x0030 //Window act width/height
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#define EBC_WIN_DSP 0x0034 //Window dsp width/height
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#define EBC_WIN_DSP_ST 0x0038 //Window display start piont
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#define EBC_INT_STATUS 0x003c //Interrupt register
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#define EBC_VCOM0 0x0040 //VCOM setting register0
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#define EBC_VCOM1 0x0044 //VCOM setting register1
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#define EBC_VCOM2 0x0048 //VCOM setting register2
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#define EBC_VCOM3 0x004c //VCOM setting register3
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#define EBC_CONFIG_DONE 0x0050 //Config done register
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#define EBC_VNUM 0x0054 //Line flag num
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#define EBC_WIN_MST2 0x0058 //Framecount memory start
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#define EBC_LUT_DATA_ADDR 0x1000 //lut data address
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#define DSP_HTOTAL(x) UPDATE(x, 27, 16)
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#define DSP_HS_END(x) UPDATE(x, 7, 0)
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#define DSP_HACT_END(x) UPDATE(x, 26, 16)
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#define DSP_HACT_ST(x) UPDATE(x, 7, 0)
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#define DSP_VTOTAL(x) UPDATE(x, 26, 16)
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#define DSP_VS_END(x) UPDATE(x, 7, 0)
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#define DSP_VACT_END(x) UPDATE(x, 26, 16)
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#define DSP_VACT_ST(x) UPDATE(x, 7, 0)
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#define DSP_HEIGHT(x) UPDATE(x, 26, 16)
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#define DSP_WIDTH(x) UPDATE(x, 11, 0)
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#define WIN2_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 27, 19)
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#define WIN_EN(x) UPDATE(x, 18, 18)
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#define BURST_REG(x) UPDATE(x, 12, 10)
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#define WIN_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 9, 2)
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#define WIN_FMT(x) UPDATE(x, 1, 0)
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#define WIN_VIR_HEIGHT(x) UPDATE(x, 31, 16)
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#define WIN_VIR_WIDTH(x) UPDATE(x, 15, 0)
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#define WIN_ACT_HEIGHT(x) UPDATE(x, 26, 16)
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#define WIN_ACT_WIDTH(x) UPDATE(x, 11, 0)
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#define WIN_DSP_HEIGHT(x) UPDATE(x, 26, 16)
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#define WIN_DSP_WIDTH(x) UPDATE(x, 11, 0)
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#define WIN_DSP_YST(x) UPDATE(x, 26, 16)
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#define WIN_DSP_XST(x) UPDATE(x, 11, 0)
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#define DSP_OUT_LOW BIT(31)
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#define DSP_EINK_MODE(x) UPDATE(x, 13, 13)
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#define DSP_EINK_MODE_MASK BIT(13)
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#define DSP_SDCE_WIDTH(x) UPDATE(x, 25, 16)
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#define DSP_FRM_TOTAL(x) UPDATE(x, 9, 2)
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#define DSP_FRM_TOTAL_MASK GENMASK(9, 2)
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#define DSP_FRM_START BIT(0)
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#define DSP_FRM_START_MASK BIT(0)
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#define SW_BURST_CTRL BIT(12)
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#define EINK_MODE_SWAP(x) UPDATE(x, 31, 31)
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#define EINK_MODE_FRM_SEL(x) UPDATE(x, 30, 30)
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#define DSP_GD_END(x) UPDATE(x, 26, 16)
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#define DSP_GD_ST(x) UPDATE(x, 15, 8)
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#define DSP_THREE_WIN_MODE(x) UPDATE(x, 7, 7)
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#define THREE_WIN_MODE_MASK BIT(7)
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#define DSP_SDDW_MODE(x) UPDATE(x, 6, 6)
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#define EPD_AUO(x) UPDATE(x, 5, 5)
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#define EPD_PWR(x) UPDATE(x, 4, 2)
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#define EPD_GDRL(x) UPDATE(x, 1, 1)
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#define EPD_SDSHR(x) UPDATE(x, 0, 0)
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#define DSP_SWAP_MODE(x) UPDATE(x, 31, 30)
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#define DSP_SDCLK_DIV(x) UPDATE(x, 19, 16)
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#define DSP_SDCLK_DIV_MASK GENMASK(19, 16)
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#define DSP_VCOM_MODE(x) UPDATE(x, 27, 27)
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#define DSP_UPDATE_MODE(x) UPDATE(x, 29, 29)
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#define DSP_DISPLAY_MODE(x) UPDATE(x, 28, 28)
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#define UPDATE_MODE_MASK BIT(29)
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#define DISPLAY_MODE_MASK BIT(28)
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#define DSP_FRM_INT_NUM(x) UPDATE(x, 19, 12)
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#define FRM_END_INT BIT(0)
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#define DSP_END_INT BIT(1)
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#define DSP_FRM_INT BIT(2)
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#define LINE_FLAG_INT BIT(3)
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#define FRM_END_INT_MASK BIT(4)
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#define DSP_END_INT_MASK BIT(5)
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#define DSP_FRM_INT_MASK BIT(6)
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#define LINE_FLAG_INT_MASK BIT(7)
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#define FRM_END_INT_CLR BIT(8)
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#define DSP_END_INT_CLR BIT(9)
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#define DSP_FRM_INT_CLR BIT(10)
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#define LINE_FLAG_INT_CLR BIT(11)
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enum ebc_win_data_fmt {
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Y_DATA_4BPP = 0,
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Y_DATA_8BPP = 1,
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RGB888 = 2,
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RGB565 = 3,
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};
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static inline void tcon_write(struct ebc_tcon *tcon, unsigned int reg,
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unsigned int value)
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{
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regmap_write(tcon->regmap_base, reg, value);
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}
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static inline unsigned int tcon_read(struct ebc_tcon *tcon, unsigned int reg)
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{
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unsigned int value;
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regmap_read(tcon->regmap_base, reg, &value);
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return value;
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}
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static inline void tcon_update_bits(struct ebc_tcon *tcon, unsigned int reg,
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unsigned int mask, unsigned int val)
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{
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regmap_update_bits(tcon->regmap_base, reg, mask, val);
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}
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static inline void tcon_cfg_done(struct ebc_tcon *tcon)
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{
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regmap_write(tcon->regmap_base, EBC_CONFIG_DONE, REG_LOAD_GLOBAL_EN);
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}
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static int tcon_enable(struct ebc_tcon *tcon, struct ebc_panel *panel)
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{
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clk_prepare_enable(tcon->hclk);
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clk_prepare_enable(tcon->dclk);
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pm_runtime_get_sync(tcon->dev);
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/* panel timing and win info config */
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tcon_write(tcon, EBC_DSP_HTIMING0,
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DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl + panel->lel) | DSP_HS_END(panel->lsl + 2));
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tcon_write(tcon, EBC_DSP_HTIMING1,
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DSP_HACT_END(panel->lsl + panel->lbl + panel->ldl) | DSP_HACT_ST(panel->lsl + panel->lbl - 1));
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tcon_write(tcon, EBC_DSP_VTIMING0,
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DSP_VTOTAL(panel->fsl + panel->fbl + panel->fdl + panel->fel) | DSP_VS_END(panel->fsl));
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tcon_write(tcon, EBC_DSP_VTIMING1,
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DSP_VACT_END(panel->fsl + panel->fbl + panel->fdl) | DSP_VACT_ST(panel->fsl + panel->fbl));
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tcon_write(tcon, EBC_DSP_ACT_INFO, DSP_HEIGHT(panel->height) | DSP_WIDTH(panel->width));
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tcon_write(tcon, EBC_WIN_VIR, WIN_VIR_HEIGHT(panel->vir_height) | WIN_VIR_WIDTH(panel->vir_width));
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tcon_write(tcon, EBC_WIN_ACT, WIN_ACT_HEIGHT(panel->height) | WIN_ACT_WIDTH(panel->width));
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tcon_write(tcon, EBC_WIN_DSP, WIN_DSP_HEIGHT(panel->height) | WIN_DSP_WIDTH(panel->width));
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tcon_write(tcon, EBC_WIN_DSP_ST, WIN_DSP_YST(panel->fsl + panel->fbl) | WIN_DSP_XST(panel->lsl + panel->lbl));
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/* win2 fifo is 512x128, win fifo is 256x128, we set fifo almost value (fifo_size - 16)
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* burst_reg = 7 mean ahb burst is incr16
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*/
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tcon_write(tcon, EBC_WIN_CTRL, WIN2_FIFO_ALMOST_FULL_LEVEL(496) | WIN_EN(1)
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| BURST_REG(7) | WIN_FIFO_ALMOST_FULL_LEVEL(240) | WIN_FMT(Y_DATA_4BPP));
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/*
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* EBC_EPD_CTRL info:
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* DSP_GD_ST: GCLK rising edge point(SCLK), which count from the rasing edge of hsync(spec is wrong, count
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* from rasing edge of hsync, not falling edge of hsync)
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* DSP_GD_END : GCLK falling edge point(SCLK), which count from the rasing edge of hsync
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* DSP_THREE_WIN_MODE: 0: lut mode or direct mode; 1: three win mode
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* DSP_SDDW_MODE: 0: 8 bit data output; 1: 16 bit data output
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* EPD_AUO: 0: EINK; 1:AUO
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* EPD_GDRL: gate scanning direction: 1: button to top 0: top to button
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* EPD_SDSHR: source scanning direction 1: right to left 0: left to right
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*/
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tcon_write(tcon, EBC_EPD_CTRL, EINK_MODE_SWAP(1)
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| DSP_GD_ST(panel->lsl + panel->gdck_sta)
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| DSP_GD_END(panel->lsl + panel->gdck_sta + panel->lgonl)
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| DSP_THREE_WIN_MODE(0)
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| DSP_SDDW_MODE(!!panel->panel_16bit)
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| EPD_AUO(0)
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| EPD_GDRL(1)
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| EPD_SDSHR(1));
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tcon_write(tcon, EBC_DSP_START, DSP_SDCE_WIDTH(panel->ldl) | SW_BURST_CTRL);
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tcon_write(tcon, EBC_DSP_CTRL,
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DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) | DSP_VCOM_MODE(1) | DSP_SDCLK_DIV(panel->panel_16bit ? 7 : 3));
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tcon_cfg_done(tcon);
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enable_irq(tcon->irq);
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return 0;
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}
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static void tcon_disable(struct ebc_tcon *tcon)
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{
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disable_irq(tcon->irq);
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/* output low */
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tcon_update_bits(tcon, EBC_DSP_START, DSP_OUT_LOW | DSP_FRM_START_MASK, DSP_OUT_LOW);
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pm_runtime_put_sync(tcon->dev);
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clk_disable_unprepare(tcon->dclk);
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clk_disable_unprepare(tcon->hclk);
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}
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static void tcon_dsp_mode_set(struct ebc_tcon *tcon, int update_mode, int display_mode, int three_win_mode, int eink_mode)
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{
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tcon_update_bits(tcon, EBC_DSP_CTRL, UPDATE_MODE_MASK | DISPLAY_MODE_MASK,
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DSP_UPDATE_MODE(!!update_mode) | DSP_DISPLAY_MODE(!!display_mode));
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tcon_update_bits(tcon, EBC_EPD_CTRL, THREE_WIN_MODE_MASK,
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DSP_THREE_WIN_MODE(!!three_win_mode));
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/* always set frm start bit 0 before real frame start */
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tcon_update_bits(tcon, EBC_DSP_START, DSP_EINK_MODE_MASK | DSP_FRM_START_MASK, DSP_EINK_MODE(!!eink_mode));
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tcon_cfg_done(tcon);
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}
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static void tcon_image_addr_set(struct ebc_tcon *tcon, u32 pre_image_addr, u32 cur_image_addr)
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{
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tcon_write(tcon, EBC_WIN_MST0, pre_image_addr);
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tcon_write(tcon, EBC_WIN_MST1, cur_image_addr);
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tcon_cfg_done(tcon);
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}
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static void tcon_frame_addr_set(struct ebc_tcon *tcon, u32 frame_addr)
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{
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tcon_write(tcon, EBC_WIN_MST2, frame_addr);
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tcon_cfg_done(tcon);
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}
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static int tcon_lut_data_set(struct ebc_tcon *tcon, unsigned int *lut_data, int frame_count, int lut_32)
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{
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int i;
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int lut_size;
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if ((!lut_32 && frame_count > 256) || (lut_32 && frame_count > 64)) {
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dev_err(tcon->dev, "frame count over flow\n");
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return -1;
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}
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if (lut_32)
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lut_size = frame_count * 64;
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else
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lut_size = frame_count * 16;
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for (i = 0; i < lut_size; i++) {
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tcon_write(tcon, EBC_LUT_DATA_ADDR + (i * 4), lut_data[i]);
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}
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tcon_cfg_done(tcon);
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return 0;
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}
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static void tcon_frame_start(struct ebc_tcon *tcon, int frame_total)
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{
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tcon_write(tcon, EBC_INT_STATUS, LINE_FLAG_INT_MASK | DSP_FRM_INT_MASK | FRM_END_INT_MASK);
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/* always set frm start bit 0 before real frame start */
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tcon_update_bits(tcon, EBC_DSP_START, DSP_FRM_TOTAL_MASK | DSP_FRM_START_MASK, DSP_FRM_TOTAL(frame_total - 1));
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tcon_cfg_done(tcon);
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tcon_update_bits(tcon, EBC_DSP_START, DSP_FRM_START_MASK, DSP_FRM_START);
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}
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static irqreturn_t tcon_irq_hanlder(int irq, void *dev_id)
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{
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struct ebc_tcon *tcon = (struct ebc_tcon *)dev_id;
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u32 intr_status;
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intr_status = tcon_read(tcon, EBC_INT_STATUS);
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if (intr_status & DSP_END_INT) {
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tcon_update_bits(tcon, EBC_INT_STATUS, DSP_END_INT_CLR, DSP_END_INT_CLR);
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if (tcon->dsp_end_callback)
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tcon->dsp_end_callback();
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}
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return IRQ_HANDLED;
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}
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static bool tcon_is_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case EBC_DSP_START:
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case EBC_EPD_CTRL:
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case EBC_DSP_CTRL:
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return false;
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}
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return true;
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}
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static struct regmap_config ebc_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.cache_type = REGCACHE_RBTREE,
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.volatile_reg = tcon_is_volatile_reg,
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};
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static int ebc_tcon_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ebc_tcon *tcon;
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struct resource *res;
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int ret;
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tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
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if (!tcon)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tcon->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(tcon->regs))
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return PTR_ERR(tcon->regs);
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tcon->len = resource_size(res);
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ebc_regmap_config.max_register = resource_size(res) - 4;
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ebc_regmap_config.name = "rockchip,ebc_tcon";
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tcon->regmap_base = devm_regmap_init_mmio(dev, tcon->regs, &ebc_regmap_config);
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if (IS_ERR(tcon->regmap_base))
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return PTR_ERR(tcon->regmap_base);
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tcon->hclk = devm_clk_get(dev, "hclk");
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if (IS_ERR(tcon->hclk)) {
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ret = PTR_ERR(tcon->hclk);
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dev_err(dev, "failed to get hclk clock: %d\n", ret);
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return ret;
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}
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tcon->dclk = devm_clk_get(dev, "dclk");
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if (IS_ERR(tcon->dclk)) {
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ret = PTR_ERR(tcon->dclk);
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dev_err(dev, "failed to get dclk clock: %d\n", ret);
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return ret;
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}
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tcon->irq = platform_get_irq(pdev, 0);
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if (tcon->irq < 0) {
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dev_err(dev, "No IRQ resource!\n");
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return tcon->irq;
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}
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irq_set_status_flags(tcon->irq, IRQ_NOAUTOEN);
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ret = devm_request_irq(dev, tcon->irq, tcon_irq_hanlder,
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0, dev_name(dev), tcon);
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if (ret < 0) {
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dev_err(dev, "failed to requeset irq: %d\n", ret);
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return ret;
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}
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tcon->dev = dev;
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tcon->enable = tcon_enable;
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tcon->disable = tcon_disable;
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tcon->dsp_mode_set = tcon_dsp_mode_set;
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tcon->image_addr_set = tcon_image_addr_set;
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tcon->frame_addr_set = tcon_frame_addr_set;
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tcon->lut_data_set = tcon_lut_data_set;
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tcon->frame_start = tcon_frame_start;
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platform_set_drvdata(pdev, tcon);
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pm_runtime_enable(dev);
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return 0;
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}
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static int ebc_tcon_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static const struct of_device_id ebc_tcon_of_match[] = {
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{ .compatible = "rockchip,rk3568-ebc-tcon" },
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{}
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};
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MODULE_DEVICE_TABLE(of, ebc_tcon_of_match);
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static struct platform_driver ebc_tcon_driver = {
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.driver = {
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.name = "rk-ebc-tcon",
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.of_match_table = ebc_tcon_of_match,
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},
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.probe = ebc_tcon_probe,
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.remove = ebc_tcon_remove,
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};
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module_platform_driver(ebc_tcon_driver);
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MODULE_AUTHOR("Zorro Liu <zorro.liu@rock-chips.com>");
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MODULE_DESCRIPTION("ROCKCHIP EBC tcon driver");
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MODULE_LICENSE("GPL v2");
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