// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
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* Author: Chris Zhong <zyw@rock-chips.com>
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*/
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/phy/phy.h>
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#include "cdn-dp-core.h"
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#include "cdn-dp-reg.h"
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static void cdn_dp_set_signal_levels(struct cdn_dp_device *dp)
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{
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struct cdn_dp_port *port = dp->port[dp->active_port];
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union phy_configure_opts phy_cfg = {0};
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u8 swing = (dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) >>
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DP_TRAIN_VOLTAGE_SWING_SHIFT;
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u8 pre_emphasis = (dp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
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>> DP_TRAIN_PRE_EMPHASIS_SHIFT;
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unsigned int lane;
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for (lane = 0; lane < dp->max_lanes; lane++) {
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phy_cfg.dp.voltage[lane] = swing;
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phy_cfg.dp.pre[lane] = pre_emphasis;
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}
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phy_cfg.dp.lanes = dp->max_lanes;
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phy_cfg.dp.link_rate = drm_dp_bw_code_to_link_rate(dp->max_rate) / 100;
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phy_cfg.dp.set_lanes = false;
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phy_cfg.dp.set_rate = false;
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phy_cfg.dp.set_voltages = true;
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phy_configure(port->phy, &phy_cfg);
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}
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static int cdn_dp_set_pattern(struct cdn_dp_device *dp, uint8_t dp_train_pat)
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{
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u32 phy_config, global_config;
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int ret;
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uint8_t pattern = dp_train_pat & DP_TRAINING_PATTERN_MASK;
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global_config = NUM_LANES(dp->max_lanes - 1) | SST_MODE |
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GLOBAL_EN | RG_EN | ENC_RST_DIS | WR_VHSYNC_FALL;
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phy_config = DP_TX_PHY_ENCODER_BYPASS(0) |
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DP_TX_PHY_SKEW_BYPASS(0) |
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DP_TX_PHY_DISPARITY_RST(0) |
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DP_TX_PHY_LANE0_SKEW(0) |
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DP_TX_PHY_LANE1_SKEW(1) |
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DP_TX_PHY_LANE2_SKEW(2) |
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DP_TX_PHY_LANE3_SKEW(3) |
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DP_TX_PHY_10BIT_ENABLE(0);
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if (pattern != DP_TRAINING_PATTERN_DISABLE) {
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global_config |= NO_VIDEO;
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phy_config |= DP_TX_PHY_TRAINING_ENABLE(1) |
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DP_TX_PHY_SCRAMBLER_BYPASS(1) |
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DP_TX_PHY_TRAINING_PATTERN(pattern);
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}
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ret = cdn_dp_reg_write(dp, DP_FRAMER_GLOBAL_CONFIG, global_config);
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if (ret) {
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DRM_ERROR("fail to set DP_FRAMER_GLOBAL_CONFIG, error: %d\n",
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ret);
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return ret;
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}
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ret = cdn_dp_reg_write(dp, DP_TX_PHY_CONFIG_REG, phy_config);
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if (ret) {
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DRM_ERROR("fail to set DP_TX_PHY_CONFIG_REG, error: %d\n",
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ret);
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return ret;
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}
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ret = cdn_dp_reg_write(dp, DPTX_LANE_EN, BIT(dp->max_lanes) - 1);
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if (ret) {
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DRM_ERROR("fail to set DPTX_LANE_EN, error: %d\n", ret);
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return ret;
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}
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if (drm_dp_enhanced_frame_cap(dp->dpcd) ||
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/*
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* A setting of 1 indicates that this is an eDP device that uses
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* only Enhanced Framing, independently of the setting by the
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* source of ENHANCED_FRAME_EN
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*/
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dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_FRAMING_CHANGE_CAP)
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ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 1);
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else
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ret = cdn_dp_reg_write(dp, DPTX_ENHNCD, 0);
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if (ret)
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DRM_ERROR("failed to set DPTX_ENHNCD, error: %x\n", ret);
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return ret;
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}
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static u8 cdn_dp_pre_emphasis_max(u8 voltage_swing)
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{
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switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
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return DP_TRAIN_PRE_EMPH_LEVEL_3;
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
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return DP_TRAIN_PRE_EMPH_LEVEL_2;
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case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
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return DP_TRAIN_PRE_EMPH_LEVEL_1;
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default:
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return DP_TRAIN_PRE_EMPH_LEVEL_0;
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}
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}
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static void cdn_dp_get_adjust_train(struct cdn_dp_device *dp,
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uint8_t link_status[DP_LINK_STATUS_SIZE])
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{
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int i;
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uint8_t v = 0, p = 0;
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uint8_t preemph_max;
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for (i = 0; i < dp->max_lanes; i++) {
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v = max(v, drm_dp_get_adjust_request_voltage(link_status, i));
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p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status,
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i));
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}
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if (v >= VOLTAGE_LEVEL_2)
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v = VOLTAGE_LEVEL_2 | DP_TRAIN_MAX_SWING_REACHED;
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preemph_max = cdn_dp_pre_emphasis_max(v);
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if (p >= preemph_max)
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p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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for (i = 0; i < dp->max_lanes; i++)
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dp->train_set[i] = v | p;
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}
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/*
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* Pick training pattern for channel equalization. Training Pattern 3 for HBR2
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* or 1.2 devices that support it, Training Pattern 2 otherwise.
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*/
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static u32 cdn_dp_select_chaneq_pattern(struct cdn_dp_device *dp)
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{
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u32 training_pattern = DP_TRAINING_PATTERN_2;
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/*
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* cdn dp support HBR2 also support TPS3. TPS3 support is also mandatory
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* for downstream devices that support HBR2. However, not all sinks
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* follow the spec.
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*/
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if (drm_dp_tps3_supported(dp->dpcd))
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training_pattern = DP_TRAINING_PATTERN_3;
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else
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DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
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return training_pattern;
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}
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static bool cdn_dp_link_max_vswing_reached(struct cdn_dp_device *dp)
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{
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int lane;
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for (lane = 0; lane < dp->max_lanes; lane++)
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if ((dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0)
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return false;
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return true;
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}
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static int cdn_dp_update_link_train(struct cdn_dp_device *dp)
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{
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int ret;
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cdn_dp_set_signal_levels(dp);
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ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
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dp->train_set, dp->max_lanes);
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if (ret != dp->max_lanes)
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return -EINVAL;
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return 0;
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}
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static int cdn_dp_set_link_train(struct cdn_dp_device *dp,
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uint8_t dp_train_pat)
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{
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uint8_t buf[sizeof(dp->train_set) + 1];
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int ret, len;
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buf[0] = dp_train_pat;
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if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
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DP_TRAINING_PATTERN_DISABLE) {
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/* don't write DP_TRAINING_LANEx_SET on disable */
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len = 1;
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} else {
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/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
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memcpy(buf + 1, dp->train_set, dp->max_lanes);
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len = dp->max_lanes + 1;
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}
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ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET,
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buf, len);
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if (ret != len)
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return -EINVAL;
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return 0;
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}
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static int cdn_dp_reset_link_train(struct cdn_dp_device *dp,
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uint8_t dp_train_pat)
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{
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int ret;
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memset(dp->train_set, 0, sizeof(dp->train_set));
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cdn_dp_set_signal_levels(dp);
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ret = cdn_dp_set_pattern(dp, dp_train_pat);
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if (ret)
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return ret;
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return cdn_dp_set_link_train(dp, dp_train_pat);
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}
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/* Enable corresponding port and start training pattern 1 */
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static int cdn_dp_link_training_clock_recovery(struct cdn_dp_device *dp)
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{
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u8 voltage;
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u8 link_status[DP_LINK_STATUS_SIZE];
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u32 voltage_tries, max_vswing_tries;
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int ret;
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/* clock recovery */
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ret = cdn_dp_reset_link_train(dp, DP_TRAINING_PATTERN_1 |
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DP_LINK_SCRAMBLING_DISABLE);
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if (ret) {
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DRM_ERROR("failed to start link train\n");
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return ret;
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}
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voltage_tries = 1;
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max_vswing_tries = 0;
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for (;;) {
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drm_dp_link_train_clock_recovery_delay(dp->dpcd);
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if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) !=
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DP_LINK_STATUS_SIZE) {
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DRM_ERROR("failed to get link status\n");
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return -EINVAL;
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}
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if (drm_dp_clock_recovery_ok(link_status, dp->max_lanes)) {
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DRM_DEBUG_KMS("clock recovery OK\n");
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return 0;
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}
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if (voltage_tries >= 5) {
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DRM_DEBUG_KMS("Same voltage tried 5 times\n");
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return -EINVAL;
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}
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if (max_vswing_tries >= 1) {
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DRM_DEBUG_KMS("Max Voltage Swing reached\n");
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return -EINVAL;
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}
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voltage = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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/* Update training set as requested by target */
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cdn_dp_get_adjust_train(dp, link_status);
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if (cdn_dp_update_link_train(dp)) {
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DRM_ERROR("failed to update link training\n");
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return -EINVAL;
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}
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if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
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voltage)
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++voltage_tries;
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else
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voltage_tries = 1;
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if (cdn_dp_link_max_vswing_reached(dp))
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++max_vswing_tries;
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}
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}
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static int cdn_dp_link_training_channel_equalization(struct cdn_dp_device *dp)
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{
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int tries, ret;
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u32 training_pattern;
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uint8_t link_status[DP_LINK_STATUS_SIZE];
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training_pattern = cdn_dp_select_chaneq_pattern(dp);
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training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
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ret = cdn_dp_set_pattern(dp, training_pattern);
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if (ret)
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return ret;
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ret = cdn_dp_set_link_train(dp, training_pattern);
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if (ret) {
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DRM_ERROR("failed to start channel equalization\n");
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return ret;
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}
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for (tries = 0; tries < 5; tries++) {
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drm_dp_link_train_channel_eq_delay(dp->dpcd);
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if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) !=
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DP_LINK_STATUS_SIZE) {
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DRM_ERROR("failed to get link status\n");
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break;
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}
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/* Make sure clock is still ok */
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if (!drm_dp_clock_recovery_ok(link_status,
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dp->max_lanes)) {
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DRM_DEBUG_KMS("Clock recovery check failed\n");
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break;
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}
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if (drm_dp_channel_eq_ok(link_status, dp->max_lanes)) {
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DRM_DEBUG_KMS("Channel EQ done\n");
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return 0;
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}
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/* Update training set as requested by target */
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cdn_dp_get_adjust_train(dp, link_status);
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if (cdn_dp_update_link_train(dp)) {
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DRM_ERROR("failed to update link training\n");
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break;
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}
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}
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/* Try 5 times, else fail and try at lower BW */
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if (tries == 5)
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DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
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return -EINVAL;
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}
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static int cdn_dp_stop_link_train(struct cdn_dp_device *dp)
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{
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int ret = cdn_dp_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
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if (ret)
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return ret;
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return cdn_dp_set_link_train(dp, DP_TRAINING_PATTERN_DISABLE);
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}
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static int cdn_dp_get_lower_link_rate(struct cdn_dp_device *dp)
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{
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switch (dp->max_rate) {
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case DP_LINK_BW_1_62:
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return -EINVAL;
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case DP_LINK_BW_2_7:
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dp->max_rate = DP_LINK_BW_1_62;
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break;
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case DP_LINK_BW_5_4:
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dp->max_rate = DP_LINK_BW_2_7;
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break;
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default:
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dp->max_rate = DP_LINK_BW_5_4;
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break;
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}
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return 0;
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}
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int cdn_dp_software_train_link(struct cdn_dp_device *dp)
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{
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struct cdn_dp_port *port = dp->port[dp->active_port];
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int ret, stop_err;
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u8 link_config[2];
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u32 rate, sink_max, source_max;
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bool ssc_on;
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ret = drm_dp_dpcd_read(&dp->aux, DP_DPCD_REV, dp->dpcd,
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sizeof(dp->dpcd));
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if (ret < 0) {
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DRM_DEV_ERROR(dp->dev, "Failed to get caps %d\n", ret);
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return ret;
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}
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source_max = dp->lanes;
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sink_max = drm_dp_max_lane_count(dp->dpcd);
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dp->max_lanes = min(source_max, sink_max);
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source_max = drm_dp_bw_code_to_link_rate(CDN_DP_MAX_LINK_RATE);
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sink_max = drm_dp_max_link_rate(dp->dpcd);
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rate = min(source_max, sink_max);
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dp->max_rate = drm_dp_link_rate_to_bw_code(rate);
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ssc_on = !!(dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
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link_config[0] = ssc_on ? DP_SPREAD_AMP_0_5 : 0;
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link_config[1] = 0;
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if (dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & 0x01)
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link_config[1] = DP_SET_ANSI_8B10B;
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drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
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while (true) {
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union phy_configure_opts phy_cfg = {0};
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phy_cfg.dp.lanes = dp->max_lanes;
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phy_cfg.dp.link_rate = drm_dp_bw_code_to_link_rate(dp->max_rate) / 100;
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phy_cfg.dp.ssc = ssc_on;
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phy_cfg.dp.set_lanes = true;
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phy_cfg.dp.set_rate = true;
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phy_cfg.dp.set_voltages = false;
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ret = phy_configure(port->phy, &phy_cfg);
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if (ret)
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return ret;
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/* Write the link configuration data */
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link_config[0] = dp->max_rate;
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link_config[1] = dp->max_lanes;
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if (drm_dp_enhanced_frame_cap(dp->dpcd))
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link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, link_config, 2);
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ret = cdn_dp_link_training_clock_recovery(dp);
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if (ret) {
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if (!cdn_dp_get_lower_link_rate(dp))
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continue;
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DRM_ERROR("training clock recovery failed: %d\n", ret);
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break;
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}
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ret = cdn_dp_link_training_channel_equalization(dp);
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if (ret) {
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if (!cdn_dp_get_lower_link_rate(dp))
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continue;
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DRM_ERROR("training channel eq failed: %d\n", ret);
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break;
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}
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break;
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}
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stop_err = cdn_dp_stop_link_train(dp);
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if (stop_err) {
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DRM_ERROR("stop training fail, error: %d\n", stop_err);
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return stop_err;
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}
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return ret;
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}
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