// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_gt_clock_utils.h"
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#define MHZ_12 12000000 /* 12MHz (24MHz/2), 83.333ns */
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#define MHZ_12_5 12500000 /* 12.5MHz (25MHz/2), 80ns */
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#define MHZ_19_2 19200000 /* 19.2MHz, 52.083ns */
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static u32 read_clock_frequency(const struct intel_gt *gt)
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{
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if (INTEL_GEN(gt->i915) >= 11) {
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u32 config;
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config = intel_uncore_read(gt->uncore, RPM_CONFIG0);
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config &= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;
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config >>= GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
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switch (config) {
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case 0: return MHZ_12;
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case 1:
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case 2: return MHZ_19_2;
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default:
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case 3: return MHZ_12_5;
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}
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} else if (INTEL_GEN(gt->i915) >= 9) {
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if (IS_GEN9_LP(gt->i915))
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return MHZ_19_2;
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else
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return MHZ_12;
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} else {
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return MHZ_12_5;
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}
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}
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void intel_gt_init_clock_frequency(struct intel_gt *gt)
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{
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/*
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* Note that on gen11+, the clock frequency may be reconfigured.
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* We do not, and we assume nobody else does.
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*/
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gt->clock_frequency = read_clock_frequency(gt);
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GT_TRACE(gt,
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"Using clock frequency: %dkHz\n",
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gt->clock_frequency / 1000);
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}
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
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void intel_gt_check_clock_frequency(const struct intel_gt *gt)
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{
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if (gt->clock_frequency != read_clock_frequency(gt)) {
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dev_err(gt->i915->drm.dev,
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"GT clock frequency changed, was %uHz, now %uHz!\n",
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gt->clock_frequency,
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read_clock_frequency(gt));
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}
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}
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#endif
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static u64 div_u64_roundup(u64 nom, u32 den)
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{
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return div_u64(nom + den - 1, den);
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}
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u32 intel_gt_clock_interval_to_ns(const struct intel_gt *gt, u32 count)
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{
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return div_u64_roundup(mul_u32_u32(count, 1000 * 1000 * 1000),
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gt->clock_frequency);
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}
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u32 intel_gt_pm_interval_to_ns(const struct intel_gt *gt, u32 count)
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{
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return intel_gt_clock_interval_to_ns(gt, 16 * count);
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}
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u32 intel_gt_ns_to_clock_interval(const struct intel_gt *gt, u32 ns)
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{
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return div_u64_roundup(mul_u32_u32(gt->clock_frequency, ns),
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1000 * 1000 * 1000);
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}
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u32 intel_gt_ns_to_pm_interval(const struct intel_gt *gt, u32 ns)
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{
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u32 val;
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/*
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* Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
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* 8300) freezing up around GPU hangs. Looks as if even
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* scheduling/timer interrupts start misbehaving if the RPS
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* EI/thresholds are "bad", leading to a very sluggish or even
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* frozen machine.
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*/
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val = DIV_ROUND_UP(intel_gt_ns_to_clock_interval(gt, ns), 16);
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if (IS_GEN(gt->i915, 6))
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val = roundup(val, 25);
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return val;
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}
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