/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_ENGINE_TYPES__
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#define __INTEL_ENGINE_TYPES__
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#include <linux/average.h>
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#include <linux/hashtable.h>
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#include <linux/irq_work.h>
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#include <linux/kref.h>
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#include <linux/list.h>
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#include <linux/llist.h>
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#include <linux/rbtree.h>
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#include <linux/timer.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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#include "i915_gem.h"
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#include "i915_pmu.h"
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#include "i915_priolist_types.h"
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#include "i915_selftest.h"
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#include "intel_breadcrumbs_types.h"
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#include "intel_sseu.h"
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#include "intel_timeline_types.h"
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#include "intel_uncore.h"
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#include "intel_wakeref.h"
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#include "intel_workarounds_types.h"
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/* Legacy HW Engine ID */
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#define RCS0_HW 0
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#define VCS0_HW 1
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#define BCS0_HW 2
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#define VECS0_HW 3
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#define VCS1_HW 4
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#define VCS2_HW 6
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#define VCS3_HW 7
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#define VECS1_HW 12
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/* Gen11+ HW Engine class + instance */
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#define RENDER_CLASS 0
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#define VIDEO_DECODE_CLASS 1
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#define VIDEO_ENHANCEMENT_CLASS 2
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#define COPY_ENGINE_CLASS 3
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#define OTHER_CLASS 4
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#define MAX_ENGINE_CLASS 4
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#define MAX_ENGINE_INSTANCE 3
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#define I915_MAX_SLICES 3
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#define I915_MAX_SUBSLICES 8
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#define I915_CMD_HASH_ORDER 9
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struct dma_fence;
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struct drm_i915_gem_object;
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struct drm_i915_reg_table;
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struct i915_gem_context;
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struct i915_request;
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struct i915_sched_attr;
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struct intel_gt;
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struct intel_ring;
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struct intel_uncore;
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typedef u8 intel_engine_mask_t;
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#define ALL_ENGINES ((intel_engine_mask_t)~0ul)
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struct intel_hw_status_page {
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struct i915_vma *vma;
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u32 *addr;
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};
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struct intel_instdone {
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u32 instdone;
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/* The following exist only in the RCS engine */
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u32 slice_common;
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u32 slice_common_extra[2];
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u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES];
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u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES];
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};
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/*
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* we use a single page to load ctx workarounds so all of these
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* values are referred in terms of dwords
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*
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* struct i915_wa_ctx_bb:
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* offset: specifies batch starting position, also helpful in case
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* if we want to have multiple batches at different offsets based on
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* some criteria. It is not a requirement at the moment but provides
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* an option for future use.
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* size: size of the batch in DWORDS
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*/
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struct i915_ctx_workarounds {
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struct i915_wa_ctx_bb {
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u32 offset;
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u32 size;
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} indirect_ctx, per_ctx;
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struct i915_vma *vma;
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};
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#define I915_MAX_VCS 4
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#define I915_MAX_VECS 2
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/*
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* Engine IDs definitions.
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* Keep instances of the same type engine together.
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*/
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enum intel_engine_id {
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RCS0 = 0,
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BCS0,
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VCS0,
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VCS1,
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VCS2,
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VCS3,
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#define _VCS(n) (VCS0 + (n))
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VECS0,
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VECS1,
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#define _VECS(n) (VECS0 + (n))
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I915_NUM_ENGINES
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#define INVALID_ENGINE ((enum intel_engine_id)-1)
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};
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/* A simple estimator for the round-trip latency of an engine */
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DECLARE_EWMA(_engine_latency, 6, 4)
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struct st_preempt_hang {
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struct completion completion;
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unsigned int count;
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};
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/**
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* struct intel_engine_execlists - execlist submission queue and port state
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*
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* The struct intel_engine_execlists represents the combined logical state of
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* driver and the hardware state for execlist mode of submission.
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*/
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struct intel_engine_execlists {
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/**
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* @tasklet: softirq tasklet for bottom handler
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*/
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struct tasklet_struct tasklet;
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/**
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* @timer: kick the current context if its timeslice expires
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*/
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struct timer_list timer;
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/**
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* @preempt: reset the current context if it fails to give way
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*/
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struct timer_list preempt;
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/**
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* @default_priolist: priority list for I915_PRIORITY_NORMAL
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*/
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struct i915_priolist default_priolist;
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/**
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* @ccid: identifier for contexts submitted to this engine
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*/
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u32 ccid;
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/**
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* @yield: CCID at the time of the last semaphore-wait interrupt.
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*
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* Instead of leaving a semaphore busy-spinning on an engine, we would
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* like to switch to another ready context, i.e. yielding the semaphore
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* timeslice.
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*/
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u32 yield;
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/**
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* @error_interrupt: CS Master EIR
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*
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* The CS generates an interrupt when it detects an error. We capture
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* the first error interrupt, record the EIR and schedule the tasklet.
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* In the tasklet, we process the pending CS events to ensure we have
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* the guilty request, and then reset the engine.
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*
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* Low 16b are used by HW, with the upper 16b used as the enabling mask.
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* Reserve the upper 16b for tracking internal errors.
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*/
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u32 error_interrupt;
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#define ERROR_CSB BIT(31)
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/**
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* @reset_ccid: Active CCID [EXECLISTS_STATUS_HI] at the time of reset
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*/
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u32 reset_ccid;
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/**
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* @no_priolist: priority lists disabled
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*/
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bool no_priolist;
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/**
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* @submit_reg: gen-specific execlist submission register
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* set to the ExecList Submission Port (elsp) register pre-Gen11 and to
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* the ExecList Submission Queue Contents register array for Gen11+
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*/
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u32 __iomem *submit_reg;
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/**
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* @ctrl_reg: the enhanced execlists control register, used to load the
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* submit queue on the HW and to request preemptions to idle
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*/
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u32 __iomem *ctrl_reg;
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#define EXECLIST_MAX_PORTS 2
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/**
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* @active: the currently known context executing on HW
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*/
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struct i915_request * const *active;
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/**
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* @inflight: the set of contexts submitted and acknowleged by HW
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*
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* The set of inflight contexts is managed by reading CS events
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* from the HW. On a context-switch event (not preemption), we
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* know the HW has transitioned from port0 to port1, and we
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* advance our inflight/active tracking accordingly.
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*/
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struct i915_request *inflight[EXECLIST_MAX_PORTS + 1 /* sentinel */];
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/**
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* @pending: the next set of contexts submitted to ELSP
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*
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* We store the array of contexts that we submit to HW (via ELSP) and
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* promote them to the inflight array once HW has signaled the
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* preemption or idle-to-active event.
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*/
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struct i915_request *pending[EXECLIST_MAX_PORTS + 1];
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/**
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* @port_mask: number of execlist ports - 1
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*/
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unsigned int port_mask;
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/**
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* @switch_priority_hint: Second context priority.
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*
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* We submit multiple contexts to the HW simultaneously and would
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* like to occasionally switch between them to emulate timeslicing.
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* To know when timeslicing is suitable, we track the priority of
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* the context submitted second.
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*/
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int switch_priority_hint;
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/**
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* @queue_priority_hint: Highest pending priority.
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*
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* When we add requests into the queue, or adjust the priority of
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* executing requests, we compute the maximum priority of those
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* pending requests. We can then use this value to determine if
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* we need to preempt the executing requests to service the queue.
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* However, since the we may have recorded the priority of an inflight
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* request we wanted to preempt but since completed, at the time of
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* dequeuing the priority hint may no longer may match the highest
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* available request priority.
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*/
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int queue_priority_hint;
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/**
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* @queue: queue of requests, in priority lists
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*/
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struct rb_root_cached queue;
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struct rb_root_cached virtual;
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/**
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* @csb_write: control register for Context Switch buffer
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*
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* Note this register may be either mmio or HWSP shadow.
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*/
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u32 *csb_write;
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/**
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* @csb_status: status array for Context Switch buffer
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*
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* Note these register may be either mmio or HWSP shadow.
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*/
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u64 *csb_status;
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/**
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* @csb_size: context status buffer FIFO size
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*/
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u8 csb_size;
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/**
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* @csb_head: context status buffer head
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*/
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u8 csb_head;
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I915_SELFTEST_DECLARE(struct st_preempt_hang preempt_hang;)
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};
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#define INTEL_ENGINE_CS_MAX_NAME 8
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struct intel_engine_cs {
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struct drm_i915_private *i915;
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struct intel_gt *gt;
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struct intel_uncore *uncore;
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char name[INTEL_ENGINE_CS_MAX_NAME];
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enum intel_engine_id id;
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enum intel_engine_id legacy_idx;
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unsigned int hw_id;
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unsigned int guc_id;
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intel_engine_mask_t mask;
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u8 class;
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u8 instance;
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u16 uabi_class;
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u16 uabi_instance;
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u32 uabi_capabilities;
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u32 context_size;
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u32 mmio_base;
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/*
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* Some w/a require forcewake to be held (which prevents RC6) while
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* a particular engine is active. If so, we set fw_domain to which
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* domains need to be held for the duration of request activity,
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* and 0 if none. We try to limit the duration of the hold as much
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* as possible.
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*/
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enum forcewake_domains fw_domain;
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atomic_t fw_active;
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unsigned long context_tag;
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struct rb_node uabi_node;
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struct intel_sseu sseu;
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struct {
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spinlock_t lock;
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struct list_head requests;
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struct list_head hold; /* ready requests, but on hold */
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} active;
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/* keep a request in reserve for a [pm] barrier under oom */
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struct i915_request *request_pool;
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struct llist_head barrier_tasks;
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struct intel_context *kernel_context; /* pinned */
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intel_engine_mask_t saturated; /* submitting semaphores too late? */
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struct {
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struct delayed_work work;
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struct i915_request *systole;
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unsigned long blocked;
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} heartbeat;
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unsigned long serial;
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unsigned long wakeref_serial;
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struct intel_wakeref wakeref;
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struct file *default_state;
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struct {
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struct intel_ring *ring;
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struct intel_timeline *timeline;
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} legacy;
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/*
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* We track the average duration of the idle pulse on parking the
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* engine to keep an estimate of the how the fast the engine is
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* under ideal conditions.
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*/
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struct ewma__engine_latency latency;
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/* Keep track of all the seqno used, a trail of breadcrumbs */
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struct intel_breadcrumbs *breadcrumbs;
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struct intel_engine_pmu {
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/**
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* @enable: Bitmask of enable sample events on this engine.
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*
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* Bits correspond to sample event types, for instance
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* I915_SAMPLE_QUEUED is bit 0 etc.
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*/
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u32 enable;
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/**
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* @enable_count: Reference count for the enabled samplers.
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*
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* Index number corresponds to @enum drm_i915_pmu_engine_sample.
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*/
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unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT];
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/**
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* @sample: Counter values for sampling events.
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*
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* Our internal timer stores the current counters in this field.
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*
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* Index number corresponds to @enum drm_i915_pmu_engine_sample.
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*/
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struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_COUNT];
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} pmu;
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struct intel_hw_status_page status_page;
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struct i915_ctx_workarounds wa_ctx;
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struct i915_wa_list ctx_wa_list;
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struct i915_wa_list wa_list;
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struct i915_wa_list whitelist;
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u32 irq_keep_mask; /* always keep these interrupts */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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void (*irq_enable)(struct intel_engine_cs *engine);
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void (*irq_disable)(struct intel_engine_cs *engine);
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void (*sanitize)(struct intel_engine_cs *engine);
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int (*resume)(struct intel_engine_cs *engine);
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struct {
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void (*prepare)(struct intel_engine_cs *engine);
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void (*rewind)(struct intel_engine_cs *engine, bool stalled);
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void (*cancel)(struct intel_engine_cs *engine);
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void (*finish)(struct intel_engine_cs *engine);
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} reset;
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void (*park)(struct intel_engine_cs *engine);
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void (*unpark)(struct intel_engine_cs *engine);
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void (*set_default_submission)(struct intel_engine_cs *engine);
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const struct intel_context_ops *cops;
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int (*request_alloc)(struct i915_request *rq);
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int (*emit_flush)(struct i915_request *request, u32 mode);
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#define EMIT_INVALIDATE BIT(0)
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#define EMIT_FLUSH BIT(1)
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#define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
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int (*emit_bb_start)(struct i915_request *rq,
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u64 offset, u32 length,
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unsigned int dispatch_flags);
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#define I915_DISPATCH_SECURE BIT(0)
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#define I915_DISPATCH_PINNED BIT(1)
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int (*emit_init_breadcrumb)(struct i915_request *rq);
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u32 *(*emit_fini_breadcrumb)(struct i915_request *rq,
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u32 *cs);
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unsigned int emit_fini_breadcrumb_dw;
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/* Pass the request to the hardware queue (e.g. directly into
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* the legacy ringbuffer or to the end of an execlist).
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*
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* This is called from an atomic context with irqs disabled; must
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* be irq safe.
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*/
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void (*submit_request)(struct i915_request *rq);
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/*
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* Called on signaling of a SUBMIT_FENCE, passing along the signaling
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* request down to the bonded pairs.
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*/
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void (*bond_execute)(struct i915_request *rq,
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struct dma_fence *signal);
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/*
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* Call when the priority on a request has changed and it and its
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* dependencies may need rescheduling. Note the request itself may
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* not be ready to run!
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*/
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void (*schedule)(struct i915_request *request,
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const struct i915_sched_attr *attr);
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void (*release)(struct intel_engine_cs *engine);
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struct intel_engine_execlists execlists;
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/*
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* Keep track of completed timelines on this engine for early
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* retirement with the goal of quickly enabling powersaving as
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* soon as the engine is idle.
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*/
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struct intel_timeline *retire;
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struct work_struct retire_work;
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/* status_notifier: list of callbacks for context-switch changes */
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struct atomic_notifier_head context_status_notifier;
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#define I915_ENGINE_USING_CMD_PARSER BIT(0)
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#define I915_ENGINE_SUPPORTS_STATS BIT(1)
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#define I915_ENGINE_HAS_PREEMPTION BIT(2)
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#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
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#define I915_ENGINE_HAS_TIMESLICES BIT(4)
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#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(5)
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#define I915_ENGINE_IS_VIRTUAL BIT(6)
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#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(7)
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#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(8)
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unsigned int flags;
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/*
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* Table of commands the command parser needs to know about
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* for this engine.
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*/
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DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
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/*
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* Table of registers allowed in commands that read/write registers.
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*/
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const struct drm_i915_reg_table *reg_tables;
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int reg_table_count;
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/*
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* Returns the bitmask for the length field of the specified command.
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* Return 0 for an unrecognized/invalid command.
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*
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* If the command parser finds an entry for a command in the engine's
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* cmd_tables, it gets the command's length based on the table entry.
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* If not, it calls this function to determine the per-engine length
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* field encoding for the command (i.e. different opcode ranges use
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* certain bits to encode the command length in the header).
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*/
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u32 (*get_cmd_length_mask)(u32 cmd_header);
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struct {
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/**
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* @active: Number of contexts currently scheduled in.
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*/
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atomic_t active;
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/**
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* @lock: Lock protecting the below fields.
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*/
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seqlock_t lock;
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/**
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* @total: Total time this engine was busy.
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*
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* Accumulated time not counting the most recent block in cases
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* where engine is currently busy (active > 0).
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*/
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ktime_t total;
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/**
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* @start: Timestamp of the last idle to active transition.
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*
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* Idle is defined as active == 0, active is active > 0.
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*/
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ktime_t start;
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/**
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* @rps: Utilisation at last RPS sampling.
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*/
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ktime_t rps;
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} stats;
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struct {
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unsigned long heartbeat_interval_ms;
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unsigned long max_busywait_duration_ns;
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unsigned long preempt_timeout_ms;
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unsigned long stop_timeout_ms;
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unsigned long timeslice_duration_ms;
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} props, defaults;
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};
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static inline bool
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intel_engine_using_cmd_parser(const struct intel_engine_cs *engine)
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{
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return engine->flags & I915_ENGINE_USING_CMD_PARSER;
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}
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static inline bool
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intel_engine_requires_cmd_parser(const struct intel_engine_cs *engine)
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{
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return engine->flags & I915_ENGINE_REQUIRES_CMD_PARSER;
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}
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static inline bool
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intel_engine_supports_stats(const struct intel_engine_cs *engine)
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{
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return engine->flags & I915_ENGINE_SUPPORTS_STATS;
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}
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static inline bool
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intel_engine_has_preemption(const struct intel_engine_cs *engine)
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{
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return engine->flags & I915_ENGINE_HAS_PREEMPTION;
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}
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static inline bool
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intel_engine_has_semaphores(const struct intel_engine_cs *engine)
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{
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return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
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}
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static inline bool
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intel_engine_has_timeslices(const struct intel_engine_cs *engine)
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{
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if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
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return false;
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return engine->flags & I915_ENGINE_HAS_TIMESLICES;
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}
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static inline bool
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intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
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{
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return engine->flags & I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
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}
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static inline bool
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intel_engine_is_virtual(const struct intel_engine_cs *engine)
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{
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return engine->flags & I915_ENGINE_IS_VIRTUAL;
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}
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static inline bool
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intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine)
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{
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return engine->flags & I915_ENGINE_HAS_RELATIVE_MMIO;
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}
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#define instdone_has_slice(dev_priv___, sseu___, slice___) \
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((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & BIT(slice___))
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#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
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(IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
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intel_sseu_has_subslice(sseu__, 0, subslice__))
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#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
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for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
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(subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
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(slice_) += ((subslice_) == 0)) \
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for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
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(instdone_has_subslice(dev_priv_, sseu_, slice_, \
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subslice_)))
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#endif /* __INTEL_ENGINE_TYPES_H__ */
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