/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_CONTEXT_TYPES__
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#define __INTEL_CONTEXT_TYPES__
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#include <linux/average.h>
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#include <linux/kref.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include "i915_active_types.h"
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#include "i915_utils.h"
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#include "intel_engine_types.h"
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#include "intel_sseu.h"
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#define CONTEXT_REDZONE POISON_INUSE
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DECLARE_EWMA(runtime, 3, 8);
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struct i915_gem_context;
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struct i915_gem_ww_ctx;
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struct i915_vma;
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struct intel_breadcrumbs;
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struct intel_context;
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struct intel_ring;
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struct intel_context_ops {
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int (*alloc)(struct intel_context *ce);
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int (*pre_pin)(struct intel_context *ce, struct i915_gem_ww_ctx *ww, void **vaddr);
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int (*pin)(struct intel_context *ce, void *vaddr);
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void (*unpin)(struct intel_context *ce);
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void (*post_unpin)(struct intel_context *ce);
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void (*enter)(struct intel_context *ce);
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void (*exit)(struct intel_context *ce);
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void (*reset)(struct intel_context *ce);
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void (*destroy)(struct kref *kref);
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};
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struct intel_context {
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/*
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* Note: Some fields may be accessed under RCU.
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*
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* Unless otherwise noted a field can safely be assumed to be protected
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* by strong reference counting.
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*/
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union {
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struct kref ref; /* no kref_get_unless_zero()! */
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struct rcu_head rcu;
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};
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struct intel_engine_cs *engine;
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struct intel_engine_cs *inflight;
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#define intel_context_inflight(ce) ptr_mask_bits(READ_ONCE((ce)->inflight), 2)
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#define intel_context_inflight_count(ce) ptr_unmask_bits(READ_ONCE((ce)->inflight), 2)
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struct i915_address_space *vm;
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struct i915_gem_context __rcu *gem_context;
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/*
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* @signal_lock protects the list of requests that need signaling,
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* @signals. While there are any requests that need signaling,
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* we add the context to the breadcrumbs worker, and remove it
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* upon completion/cancellation of the last request.
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*/
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struct list_head signal_link; /* Accessed under RCU */
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struct list_head signals; /* Guarded by signal_lock */
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spinlock_t signal_lock; /* protects signals, the list of requests */
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struct i915_vma *state;
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struct intel_ring *ring;
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struct intel_timeline *timeline;
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unsigned long flags;
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#define CONTEXT_BARRIER_BIT 0
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#define CONTEXT_ALLOC_BIT 1
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#define CONTEXT_VALID_BIT 2
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#define CONTEXT_CLOSED_BIT 3
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#define CONTEXT_USE_SEMAPHORES 4
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#define CONTEXT_BANNED 5
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#define CONTEXT_FORCE_SINGLE_SUBMISSION 6
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#define CONTEXT_NOPREEMPT 7
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u32 *lrc_reg_state;
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union {
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struct {
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u32 lrca;
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u32 ccid;
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};
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u64 desc;
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} lrc;
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u32 tag; /* cookie passed to HW to track this context on submission */
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/* Time on GPU as tracked by the hw. */
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struct {
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struct ewma_runtime avg;
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u64 total;
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u32 last;
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I915_SELFTEST_DECLARE(u32 num_underflow);
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I915_SELFTEST_DECLARE(u32 max_underflow);
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} runtime;
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unsigned int active_count; /* protected by timeline->mutex */
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atomic_t pin_count;
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struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
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/**
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* active: Active tracker for the rq activity (inc. external) on this
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* intel_context object.
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*/
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struct i915_active active;
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const struct intel_context_ops *ops;
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/** sseu: Control eu/slice partitioning */
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struct intel_sseu sseu;
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u8 wa_bb_page; /* if set, page num reserved for context workarounds */
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};
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#endif /* __INTEL_CONTEXT_TYPES__ */
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