// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_vma.h"
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#include "intel_context.h"
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#include "intel_engine_pm.h"
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#include "intel_gpu_commands.h"
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#include "intel_lrc.h"
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#include "intel_lrc_reg.h"
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#include "intel_ring.h"
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#include "intel_sseu.h"
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static int gen8_emit_rpcs_config(struct i915_request *rq,
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const struct intel_context *ce,
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const struct intel_sseu sseu)
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{
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u64 offset;
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u32 *cs;
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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offset = i915_ggtt_offset(ce->state) +
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LRC_STATE_OFFSET + CTX_R_PWR_CLK_STATE * 4;
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*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
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*cs++ = lower_32_bits(offset);
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*cs++ = upper_32_bits(offset);
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*cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu);
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intel_ring_advance(rq, cs);
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return 0;
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}
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static int
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gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu)
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{
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struct i915_request *rq;
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int ret;
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lockdep_assert_held(&ce->pin_mutex);
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/*
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* If the context is not idle, we have to submit an ordered request to
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* modify its context image via the kernel context (writing to our own
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* image, or into the registers directory, does not stick). Pristine
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* and idle contexts will be configured on pinning.
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*/
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if (!intel_context_pin_if_active(ce))
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return 0;
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rq = intel_engine_create_kernel_request(ce->engine);
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if (IS_ERR(rq)) {
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ret = PTR_ERR(rq);
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goto out_unpin;
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}
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/* Serialise with the remote context */
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ret = intel_context_prepare_remote_request(ce, rq);
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if (ret == 0)
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ret = gen8_emit_rpcs_config(rq, ce, sseu);
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i915_request_add(rq);
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out_unpin:
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intel_context_unpin(ce);
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return ret;
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}
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int
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intel_context_reconfigure_sseu(struct intel_context *ce,
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const struct intel_sseu sseu)
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{
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int ret;
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GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);
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ret = intel_context_lock_pinned(ce);
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if (ret)
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return ret;
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/* Nothing to do if unmodified. */
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if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))
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goto unlock;
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ret = gen8_modify_rpcs(ce, sseu);
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if (!ret)
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ce->sseu = sseu;
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unlock:
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intel_context_unlock_pinned(ce);
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return ret;
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}
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