/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2016 Intel Corporation
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*/
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#include "display/intel_frontbuffer.h"
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#include "i915_drv.h"
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#include "i915_gem_clflush.h"
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#include "i915_sw_fence_work.h"
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#include "i915_trace.h"
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struct clflush {
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struct dma_fence_work base;
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struct drm_i915_gem_object *obj;
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};
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static void __do_clflush(struct drm_i915_gem_object *obj)
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{
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GEM_BUG_ON(!i915_gem_object_has_pages(obj));
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drm_clflush_sg(obj->mm.pages);
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i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
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}
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static int clflush_work(struct dma_fence_work *base)
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{
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struct clflush *clflush = container_of(base, typeof(*clflush), base);
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struct drm_i915_gem_object *obj = clflush->obj;
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int err;
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err = i915_gem_object_pin_pages(obj);
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if (err)
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return err;
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__do_clflush(obj);
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i915_gem_object_unpin_pages(obj);
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return 0;
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}
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static void clflush_release(struct dma_fence_work *base)
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{
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struct clflush *clflush = container_of(base, typeof(*clflush), base);
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i915_gem_object_put(clflush->obj);
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}
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static const struct dma_fence_work_ops clflush_ops = {
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.name = "clflush",
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.work = clflush_work,
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.release = clflush_release,
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};
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static struct clflush *clflush_work_create(struct drm_i915_gem_object *obj)
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{
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struct clflush *clflush;
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GEM_BUG_ON(!obj->cache_dirty);
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clflush = kmalloc(sizeof(*clflush), GFP_KERNEL);
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if (!clflush)
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return NULL;
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dma_fence_work_init(&clflush->base, &clflush_ops);
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clflush->obj = i915_gem_object_get(obj); /* obj <-> clflush cycle */
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return clflush;
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}
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bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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unsigned int flags)
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{
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struct clflush *clflush;
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assert_object_held(obj);
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/*
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* Stolen memory is always coherent with the GPU as it is explicitly
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* marked as wc by the system, or the system is cache-coherent.
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* Similarly, we only access struct pages through the CPU cache, so
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* anything not backed by physical memory we consider to be always
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* coherent and not need clflushing.
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*/
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if (!i915_gem_object_has_struct_page(obj)) {
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obj->cache_dirty = false;
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return false;
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}
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/* If the GPU is snooping the contents of the CPU cache,
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* we do not need to manually clear the CPU cache lines. However,
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* the caches are only snooped when the render cache is
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* flushed/invalidated. As we always have to emit invalidations
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* and flushes when moving into and out of the RENDER domain, correct
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* snooping behaviour occurs naturally as the result of our domain
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* tracking.
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*/
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if (!(flags & I915_CLFLUSH_FORCE) &&
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obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
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return false;
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trace_i915_gem_object_clflush(obj);
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clflush = NULL;
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if (!(flags & I915_CLFLUSH_SYNC))
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clflush = clflush_work_create(obj);
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if (clflush) {
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i915_sw_fence_await_reservation(&clflush->base.chain,
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obj->base.resv, NULL, true,
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i915_fence_timeout(to_i915(obj->base.dev)),
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I915_FENCE_GFP);
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dma_resv_add_excl_fence(obj->base.resv, &clflush->base.dma);
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dma_fence_work_commit(&clflush->base);
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} else if (obj->mm.pages) {
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__do_clflush(obj);
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} else {
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GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
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}
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obj->cache_dirty = false;
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return true;
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}
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