/* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef _INTEL_DSB_H
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#define _INTEL_DSB_H
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#include <linux/types.h>
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#include "i915_reg.h"
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struct intel_crtc_state;
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struct i915_vma;
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enum dsb_id {
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INVALID_DSB = -1,
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DSB1,
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DSB2,
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DSB3,
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MAX_DSB_PER_PIPE
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};
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struct intel_dsb {
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enum dsb_id id;
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u32 *cmd_buf;
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struct i915_vma *vma;
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/*
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* free_pos will point the first free entry position
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* and help in calculating tail of command buffer.
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*/
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int free_pos;
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/*
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* ins_start_offset will help to store start address of the dsb
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* instuction and help in identifying the batch of auto-increment
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* register.
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*/
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u32 ins_start_offset;
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};
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void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
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void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
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void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
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i915_reg_t reg, u32 val);
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void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
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i915_reg_t reg, u32 val);
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void intel_dsb_commit(const struct intel_crtc_state *crtc_state);
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#endif
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