/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_BW_H__
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#define __INTEL_BW_H__
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#include <drm/drm_atomic.h>
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#include "intel_display.h"
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#include "intel_display_power.h"
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#include "intel_global_state.h"
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_dbuf_bw {
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int used_bw[I915_MAX_DBUF_SLICES];
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};
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struct intel_bw_state {
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struct intel_global_state base;
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struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
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/*
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* Contains a bit mask, used to determine, whether correspondent
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* pipe allows SAGV or not.
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*/
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u8 pipe_sagv_reject;
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/*
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* Current QGV points mask, which restricts
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* some particular SAGV states, not to confuse
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* with pipe_sagv_mask.
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*/
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u8 qgv_points_mask;
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unsigned int data_rate[I915_MAX_PIPES];
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u8 num_active_planes[I915_MAX_PIPES];
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/* bitmask of active pipes */
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u8 active_pipes;
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int min_cdclk;
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};
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#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)
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struct intel_bw_state *
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intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
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struct intel_bw_state *
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intel_atomic_get_new_bw_state(struct intel_atomic_state *state);
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struct intel_bw_state *
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intel_atomic_get_bw_state(struct intel_atomic_state *state);
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void intel_bw_init_hw(struct drm_i915_private *dev_priv);
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int intel_bw_init(struct drm_i915_private *dev_priv);
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int intel_bw_atomic_check(struct intel_atomic_state *state);
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void intel_bw_crtc_update(struct intel_bw_state *bw_state,
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const struct intel_crtc_state *crtc_state);
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int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
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u32 points_mask);
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int intel_bw_calc_min_cdclk(struct intel_atomic_state *state);
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int skl_bw_calc_min_cdclk(struct intel_atomic_state *state);
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#endif /* __INTEL_BW_H__ */
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