// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Broadcom
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/bcm2835-aux.h>
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#define BCM2835_AUXIRQ 0x00
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#define BCM2835_AUXENB 0x04
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static int bcm2835_aux_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct clk_hw_onecell_data *onecell;
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const char *parent;
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struct clk *parent_clk;
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void __iomem *reg, *gate;
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parent_clk = devm_clk_get(dev, NULL);
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if (IS_ERR(parent_clk))
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return PTR_ERR(parent_clk);
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parent = __clk_get_name(parent_clk);
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reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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onecell = devm_kmalloc(dev,
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struct_size(onecell, hws,
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BCM2835_AUX_CLOCK_COUNT),
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GFP_KERNEL);
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if (!onecell)
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return -ENOMEM;
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onecell->num = BCM2835_AUX_CLOCK_COUNT;
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gate = reg + BCM2835_AUXENB;
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onecell->hws[BCM2835_AUX_CLOCK_UART] =
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clk_hw_register_gate(dev, "aux_uart", parent, 0, gate, 0, 0, NULL);
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onecell->hws[BCM2835_AUX_CLOCK_SPI1] =
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clk_hw_register_gate(dev, "aux_spi1", parent, 0, gate, 1, 0, NULL);
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onecell->hws[BCM2835_AUX_CLOCK_SPI2] =
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clk_hw_register_gate(dev, "aux_spi2", parent, 0, gate, 2, 0, NULL);
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return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
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onecell);
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}
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static const struct of_device_id bcm2835_aux_clk_of_match[] = {
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{ .compatible = "brcm,bcm2835-aux", },
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{},
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};
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MODULE_DEVICE_TABLE(of, bcm2835_aux_clk_of_match);
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static struct platform_driver bcm2835_aux_clk_driver = {
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.driver = {
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.name = "bcm2835-aux-clk",
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.of_match_table = bcm2835_aux_clk_of_match,
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},
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.probe = bcm2835_aux_clk_probe,
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};
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builtin_platform_driver(bcm2835_aux_clk_driver);
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MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
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MODULE_DESCRIPTION("BCM2835 auxiliary peripheral clock driver");
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MODULE_LICENSE("GPL");
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