/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __ASM_POWERPC_PCI_H
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#define __ASM_POWERPC_PCI_H
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#ifdef __KERNEL__
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/*
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*/
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/dma-map-ops.h>
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#include <linux/scatterlist.h>
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#include <asm/machdep.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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/* Return values for pci_controller_ops.probe_mode function */
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#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
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#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
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#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x10000000
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/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
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#define IOBASE_BRIDGE_NUMBER 0
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#define IOBASE_MEMORY 1
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#define IOBASE_IO 2
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#define IOBASE_ISA_IO 3
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#define IOBASE_ISA_MEM 4
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/*
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* Set this to 1 if you want the kernel to re-assign all PCI
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* bus numbers (don't do that on ppc64 yet !)
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*/
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#define pcibios_assign_all_busses() \
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(pci_has_flag(PCI_REASSIGN_ALL_BUS))
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#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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if (ppc_md.pci_get_legacy_ide_irq)
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return ppc_md.pci_get_legacy_ide_irq(dev, channel);
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return channel ? 15 : 14;
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}
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#ifdef CONFIG_PCI
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extern void set_pci_dma_ops(const struct dma_map_ops *dma_ops);
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#else /* CONFIG_PCI */
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#define set_pci_dma_ops(d)
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#endif
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#ifdef CONFIG_PPC64
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/*
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* We want to avoid touching the cacheline size or MWI bit.
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* pSeries firmware sets the cacheline size (which is not the cpu cacheline
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* size in all cases) and hardware treats MWI the same as memory write.
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*/
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#define PCI_DISABLE_MWI
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#endif /* CONFIG_PPC64 */
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extern int pci_domain_nr(struct pci_bus *bus);
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/* Decide whether to display the domain number in /proc */
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extern int pci_proc_domain(struct pci_bus *bus);
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struct vm_area_struct;
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/* Tell PCI code what kind of PCI resource mappings we support */
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#define HAVE_PCI_MMAP 1
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#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
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#define arch_can_pci_mmap_io() 1
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#define arch_can_pci_mmap_wc() 1
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extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
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size_t count);
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extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
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size_t count);
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extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
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struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state);
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#define HAVE_PCI_LEGACY 1
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extern void pcibios_claim_one_bus(struct pci_bus *b);
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extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
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extern void pcibios_resource_survey(void);
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extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
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extern int remove_phb_dynamic(struct pci_controller *phb);
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extern struct pci_dev *of_create_pci_dev(struct device_node *node,
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struct pci_bus *bus, int devfn);
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extern unsigned int pci_parse_of_flags(u32 addr0, int bridge);
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extern void of_scan_pci_bridge(struct pci_dev *dev);
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extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
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extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
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struct file;
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extern pgprot_t pci_phys_mem_access_prot(struct file *file,
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unsigned long pfn,
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unsigned long size,
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pgprot_t prot);
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extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
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extern void pcibios_setup_bus_self(struct pci_bus *bus);
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extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
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extern void pcibios_scan_phb(struct pci_controller *hose);
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#endif /* __KERNEL__ */
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extern struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev);
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extern struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index);
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extern int pnv_npu2_init(struct pci_controller *hose);
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extern int pnv_npu2_map_lpar_dev(struct pci_dev *gpdev, unsigned int lparid,
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unsigned long msr);
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extern int pnv_npu2_unmap_lpar_dev(struct pci_dev *gpdev);
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#endif /* __ASM_POWERPC_PCI_H */
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