/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_PARISC_ROPES_H_
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#define _ASM_PARISC_ROPES_H_
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#include <asm/parisc-device.h>
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#ifdef CONFIG_64BIT
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/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
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#define ZX1_SUPPORT
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#endif
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#ifdef CONFIG_PROC_FS
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/* depends on proc fs support. But costs CPU performance */
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#undef SBA_COLLECT_STATS
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#endif
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/*
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** The number of pdir entries to "free" before issuing
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** a read to PCOM register to flush out PCOM writes.
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** Interacts with allocation granularity (ie 4 or 8 entries
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** allocated and free'd/purged at a time might make this
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** less interesting).
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*/
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#define DELAYED_RESOURCE_CNT 16
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#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
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#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
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struct ioc {
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void __iomem *ioc_hpa; /* I/O MMU base address */
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char *res_map; /* resource map, bit == pdir entry */
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u64 *pdir_base; /* physical base address */
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unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
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unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
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#ifdef ZX1_SUPPORT
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unsigned long iovp_mask; /* help convert IOVA to IOVP */
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#endif
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unsigned long *res_hint; /* next avail IOVP - circular search */
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spinlock_t res_lock;
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unsigned int res_bitshift; /* from the LEFT! */
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unsigned int res_size; /* size of resource map in bytes */
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#ifdef SBA_HINT_SUPPORT
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/* FIXME : DMA HINTs not used */
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unsigned long hint_mask_pdir; /* bits used for DMA hints */
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unsigned int hint_shift_pdir;
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#endif
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#if DELAYED_RESOURCE_CNT > 0
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int saved_cnt;
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struct sba_dma_pair {
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dma_addr_t iova;
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size_t size;
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} saved[DELAYED_RESOURCE_CNT];
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#endif
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#ifdef SBA_COLLECT_STATS
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#define SBA_SEARCH_SAMPLE 0x100
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unsigned long avg_search[SBA_SEARCH_SAMPLE];
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unsigned long avg_idx; /* current index into avg_search */
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unsigned long used_pages;
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unsigned long msingle_calls;
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unsigned long msingle_pages;
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unsigned long msg_calls;
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unsigned long msg_pages;
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unsigned long usingle_calls;
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unsigned long usingle_pages;
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unsigned long usg_calls;
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unsigned long usg_pages;
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#endif
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/* STUFF We don't need in performance path */
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unsigned int pdir_size; /* in bytes, determined by IOV Space size */
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};
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struct sba_device {
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struct sba_device *next; /* list of SBA's in system */
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struct parisc_device *dev; /* dev found in bus walk */
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const char *name;
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void __iomem *sba_hpa; /* base address */
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spinlock_t sba_lock;
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unsigned int flags; /* state/functionality enabled */
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unsigned int hw_rev; /* HW revision of chip */
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struct resource chip_resv; /* MMIO reserved for chip */
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struct resource iommu_resv; /* MMIO reserved for iommu */
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unsigned int num_ioc; /* number of on-board IOC's */
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struct ioc ioc[MAX_IOC];
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};
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#define ASTRO_RUNWAY_PORT 0x582
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#define IKE_MERCED_PORT 0x803
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#define REO_MERCED_PORT 0x804
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#define REOG_MERCED_PORT 0x805
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#define PLUTO_MCKINLEY_PORT 0x880
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static inline int IS_ASTRO(struct parisc_device *d) {
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return d->id.hversion == ASTRO_RUNWAY_PORT;
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}
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static inline int IS_IKE(struct parisc_device *d) {
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return d->id.hversion == IKE_MERCED_PORT;
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}
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static inline int IS_PLUTO(struct parisc_device *d) {
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return d->id.hversion == PLUTO_MCKINLEY_PORT;
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}
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#define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */
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#define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */
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#define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2)
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#define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
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#define SBA_AGPGART_COOKIE 0x0000badbadc0ffeeULL
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#define SBA_FUNC_ID 0x0000 /* function id */
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#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
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#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
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#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
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#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
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/* Ike's IOC's occupy functions 2 and 3 */
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#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
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#define IOC_CTRL 0x8 /* IOC_CTRL offset */
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#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
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#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
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#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
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#define IOC_CTRL_RM (1 << 8) /* Real Mode */
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#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
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#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
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#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
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/*
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** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
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** Firmware programs this stuff. Don't touch it.
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*/
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#define LMMIO_DIRECT0_BASE 0x300
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#define LMMIO_DIRECT0_MASK 0x308
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#define LMMIO_DIRECT0_ROUTE 0x310
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#define LMMIO_DIST_BASE 0x360
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#define LMMIO_DIST_MASK 0x368
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#define LMMIO_DIST_ROUTE 0x370
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#define IOS_DIST_BASE 0x390
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#define IOS_DIST_MASK 0x398
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#define IOS_DIST_ROUTE 0x3A0
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#define IOS_DIRECT_BASE 0x3C0
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#define IOS_DIRECT_MASK 0x3C8
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#define IOS_DIRECT_ROUTE 0x3D0
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/*
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** Offsets into I/O TLB (Function 2 and 3 on Ike)
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*/
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#define ROPE0_CTL 0x200 /* "regbus pci0" */
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#define ROPE1_CTL 0x208
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#define ROPE2_CTL 0x210
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#define ROPE3_CTL 0x218
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#define ROPE4_CTL 0x220
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#define ROPE5_CTL 0x228
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#define ROPE6_CTL 0x230
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#define ROPE7_CTL 0x238
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#define IOC_ROPE0_CFG 0x500 /* pluto only */
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#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
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#define HF_ENABLE 0x40
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#define IOC_IBASE 0x300 /* IO TLB */
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#define IOC_IMASK 0x308
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#define IOC_PCOM 0x310
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#define IOC_TCNFG 0x318
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#define IOC_PDIR_BASE 0x320
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/*
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** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
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** It's safer (avoid memory corruption) to keep DMA page mappings
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** equivalently sized to VM PAGE_SIZE.
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**
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** We really can't avoid generating a new mapping for each
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** page since the Virtual Coherence Index has to be generated
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** and updated for each page.
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**
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** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
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*/
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#define IOVP_SIZE PAGE_SIZE
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#define IOVP_SHIFT PAGE_SHIFT
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#define IOVP_MASK PAGE_MASK
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#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
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#define SBA_PERF_MASK1 0x718
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#define SBA_PERF_MASK2 0x730
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/*
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** Offsets into PCI Performance Counters (functions 12 and 13)
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** Controlled by PERF registers in function 2 & 3 respectively.
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*/
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#define SBA_PERF_CNT1 0x200
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#define SBA_PERF_CNT2 0x208
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#define SBA_PERF_CNT3 0x210
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/*
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** lba_device: Per instance Elroy data structure
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*/
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struct lba_device {
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struct pci_hba_data hba;
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spinlock_t lba_lock;
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void *iosapic_obj;
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#ifdef CONFIG_64BIT
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void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */
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#endif
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int flags; /* state/functionality enabled */
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int hw_rev; /* HW revision of chip */
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};
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#define ELROY_HVERS 0x782
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#define MERCURY_HVERS 0x783
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#define QUICKSILVER_HVERS 0x784
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static inline int IS_ELROY(struct parisc_device *d) {
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return (d->id.hversion == ELROY_HVERS);
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}
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static inline int IS_MERCURY(struct parisc_device *d) {
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return (d->id.hversion == MERCURY_HVERS);
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}
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static inline int IS_QUICKSILVER(struct parisc_device *d) {
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return (d->id.hversion == QUICKSILVER_HVERS);
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}
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static inline int agp_mode_mercury(void __iomem *hpa) {
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u64 bus_mode;
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bus_mode = readl(hpa + 0x0620);
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if (bus_mode & 1)
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return 1;
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return 0;
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}
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/*
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** I/O SAPIC init function
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** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC.
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** Call setup as part of per instance initialization.
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** (ie *not* init_module() function unless only one is present.)
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** fixup_irq is to initialize PCI IRQ line support and
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** virtualize pcidev->irq value. To be called by pci_fixup_bus().
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*/
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extern void *iosapic_register(unsigned long hpa);
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extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
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#define LBA_FUNC_ID 0x0000 /* function id */
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#define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
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#define LBA_CAPABLE 0x0030 /* capabilities register */
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#define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
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#define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
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#define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
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#define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
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#define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
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#define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
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#define LBA_ARB_PRI 0x0088 /* firmware sets this. */
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#define LBA_ARB_MODE 0x0090 /* firmware sets this. */
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#define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
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#define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
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#define LBA_STAT_CTL 0x0108 /* Status & Control */
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#define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
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#define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
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#define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
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#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
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#define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
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#define LBA_LMMIO_MASK 0x0208
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#define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
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#define LBA_GMMIO_MASK 0x0218
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#define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
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#define LBA_WLMMIO_MASK 0x0228
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#define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
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#define LBA_WGMMIO_MASK 0x0238
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#define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
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#define LBA_IOS_MASK 0x0248
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#define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
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#define LBA_ELMMIO_MASK 0x0258
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#define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
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#define LBA_EIOS_MASK 0x0268
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#define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
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#define LBA_DMA_CTL 0x0278 /* firmware sets this */
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#define LBA_IBASE 0x0300 /* SBA DMA support */
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#define LBA_IMASK 0x0308
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/* FIXME: ignore DMA Hint stuff until we can measure performance */
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#define LBA_HINT_CFG 0x0310
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#define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
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#define LBA_BUS_MODE 0x0620
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/* ERROR regs are needed for config cycle kluges */
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#define LBA_ERROR_CONFIG 0x0680
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#define LBA_SMART_MODE 0x20
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#define LBA_ERROR_STATUS 0x0688
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#define LBA_ROPE_CTL 0x06A0
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#define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
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#endif /*_ASM_PARISC_ROPES_H_*/
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