/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* TXx9 SoC DMA Controller
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*/
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#ifndef __ASM_TXX9_DMAC_H
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#define __ASM_TXX9_DMAC_H
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#include <linux/dmaengine.h>
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#define TXX9_DMA_MAX_NR_CHANNELS 4
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/**
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* struct txx9dmac_platform_data - Controller configuration parameters
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* @memcpy_chan: Channel used for DMA_MEMCPY
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* @have_64bit_regs: DMAC have 64 bit registers
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*/
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struct txx9dmac_platform_data {
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int memcpy_chan;
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bool have_64bit_regs;
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};
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/**
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* struct txx9dmac_chan_platform_data - Channel configuration parameters
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* @dmac_dev: A platform device for DMAC
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*/
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struct txx9dmac_chan_platform_data {
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struct platform_device *dmac_dev;
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};
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/**
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* struct txx9dmac_slave - Controller-specific information about a slave
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* @tx_reg: physical address of data register used for
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* memory-to-peripheral transfers
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* @rx_reg: physical address of data register used for
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* peripheral-to-memory transfers
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* @reg_width: peripheral register width
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*/
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struct txx9dmac_slave {
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u64 tx_reg;
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u64 rx_reg;
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unsigned int reg_width;
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};
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void txx9_dmac_init(int id, unsigned long baseaddr, int irq,
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const struct txx9dmac_platform_data *pdata);
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#endif /* __ASM_TXX9_DMAC_H */
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