/*
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* Mbus-L to Mbus Bridge Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include "dove.h"
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#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
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#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
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#define CPU_CTRL_PCIE0_LINK 0x00000001
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#define CPU_RESET 0x00000002
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#define CPU_CTRL_PCIE1_LINK 0x00000008
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define FIQ_MASK_LOW_OFF 0x0008
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#define ENDPOINT_MASK_LOW_OFF 0x000c
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#define IRQ_CAUSE_HIGH_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define FIQ_MASK_HIGH_OFF 0x0018
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#define ENDPOINT_MASK_HIGH_OFF 0x001c
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#define PCIE_INTERRUPT_MASK_OFF 0x0020
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#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
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#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
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#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
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#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
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#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
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#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
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#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
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#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
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#endif
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