/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ARM_CACHETYPE_H
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#define __ASM_ARM_CACHETYPE_H
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#define CACHEID_VIVT (1 << 0)
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#define CACHEID_VIPT_NONALIASING (1 << 1)
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#define CACHEID_VIPT_ALIASING (1 << 2)
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#define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
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#define CACHEID_ASID_TAGGED (1 << 3)
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#define CACHEID_VIPT_I_ALIASING (1 << 4)
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#define CACHEID_PIPT (1 << 5)
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extern unsigned int cacheid;
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#define cache_is_vivt() cacheid_is(CACHEID_VIVT)
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#define cache_is_vipt() cacheid_is(CACHEID_VIPT)
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#define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING)
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#define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING)
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#define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED)
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#define icache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_I_ALIASING)
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#define icache_is_pipt() cacheid_is(CACHEID_PIPT)
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/*
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* __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
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* Mask out support which will never be present on newer CPUs.
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* - v6+ is never VIVT
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* - v7+ VIPT never aliases on D-side
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*/
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#if __LINUX_ARM_ARCH__ >= 7
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#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING |\
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CACHEID_ASID_TAGGED |\
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CACHEID_VIPT_I_ALIASING |\
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CACHEID_PIPT)
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#elif __LINUX_ARM_ARCH__ >= 6
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#define __CACHEID_ARCH_MIN (~CACHEID_VIVT)
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#else
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#define __CACHEID_ARCH_MIN (~0)
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#endif
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/*
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* Mask out support which isn't configured
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*/
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#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
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#define __CACHEID_ALWAYS (CACHEID_VIVT)
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#define __CACHEID_NEVER (~CACHEID_VIVT)
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#elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
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#define __CACHEID_ALWAYS (0)
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#define __CACHEID_NEVER (CACHEID_VIVT)
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#else
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#define __CACHEID_ALWAYS (0)
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#define __CACHEID_NEVER (0)
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#endif
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static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
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{
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return (__CACHEID_ALWAYS & mask) |
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(~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
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}
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#define CSSELR_ICACHE 1
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#define CSSELR_DCACHE 0
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#define CSSELR_L1 (0 << 1)
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#define CSSELR_L2 (1 << 1)
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#define CSSELR_L3 (2 << 1)
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#define CSSELR_L4 (3 << 1)
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#define CSSELR_L5 (4 << 1)
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#define CSSELR_L6 (5 << 1)
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#define CSSELR_L7 (6 << 1)
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#ifndef CONFIG_CPU_V7M
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static inline void set_csselr(unsigned int cache_selector)
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{
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asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
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}
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static inline unsigned int read_ccsidr(void)
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{
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unsigned int val;
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asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
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return val;
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}
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#else /* CONFIG_CPU_V7M */
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#include <linux/io.h>
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#include "asm/v7m.h"
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static inline void set_csselr(unsigned int cache_selector)
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{
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writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
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}
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static inline unsigned int read_ccsidr(void)
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{
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return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
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}
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#endif
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#endif
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