// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*/
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/ {
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memory: memory {
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device_type = "memory";
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reg = <0x00000000 0x08000000>;
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};
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ramdisk: ramdisk {
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compatible = "rockchip,ramdisk";
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memory-region = <&ramdisk_r>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rtos: rtos@40000 {
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reg = <0x40000 0x40000>;
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};
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meta: meta@800000 {
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/* reg's offset MUST match with RTOS */
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reg = <0x00800000 0x60000>;
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};
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rkisp_thunderboot: rkisp@860000 {
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/* reg's offset MUST match with RTOS */
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/*
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* vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
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* e.g. 1920x1080: 0xa8c000
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*/
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reg = <0x00860000 0xa8c000>;
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};
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ramdisk_r: ramdisk_r {
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reg = <0x12ec000 (10 * 0x00100000)>;
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};
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ramdisk_c: ramdisk_c {
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reg = <0x1cec000 (5 * 0x00100000)>;
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};
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rkisp1_thunderboot: rkisp1_thunderboot {
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/* vicap capture for other camera */
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};
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};
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thunder_boot_rkisp: thunder-boot-rkisp {
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compatible = "rockchip,thunder-boot-rkisp";
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clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>,
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<&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>,
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<&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
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<&cru DCLK_VICAP>, <&cru PCLK_VICAP>,
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<&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>,
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<&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>,
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<&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>,
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<&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>,
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<&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>,
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<&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>,
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<&cru CLK_I2C4>, <&cru PCLK_I2C4>;
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clock-names = "aclk_isp", "hclk_isp",
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"clk_isp_core", "clk_isp_core_vicap",
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"aclk_cif","hclk_cif",
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"dclk_cif", "pclk_cif",
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"i0clk_cif", "i1clk_cif",
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"rx0clk_cif", "rx1clk_cif",
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"isp0clk_cif", "sclk_m0_cif",
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"sclk_m1_cif", "pclk_vepu_cif",
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"pclk_csi2host0", "clk_rxbyte_hs0",
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"pclk_csi2host1", "clk_rxbyte_hs1",
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"i2c", "pclk";
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status = "okay";
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};
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thunder_boot_service: thunder-boot-service {
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compatible = "rockchip,thunder-boot-service";
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mbox-names = "amp-rx";
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mboxes = <&mailbox 1>;
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resets = <&cru SRST_CORE_MCU>, <&cru SRST_CORE_MCU_PWRUP>,
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<&cru SRST_CORE_MCU_CPU>, <&cru SRST_T_CORE_MCU_CPU>;
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reset-names = "core_mcu", "core_mcu_pwrup",
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"core_mcu_cpu", "t_core_mcu_cpu";
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memory-region = <&rtos>;
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status = "disabled";
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};
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};
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&hw_decompress {
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status = "okay";
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memory-region = <&ramdisk_c>;
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};
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&rkisp_vir0 {
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memory-region-thunderboot = <&rkisp_thunderboot>;
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};
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&rkvenc {
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assigned-clocks = <&cru CLK_CORE_VEPU>;
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assigned-clock-rates = <410000000>;
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};
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