/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT).
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*/
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#include <dt-bindings/soc/rockchip-system-status.h>
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#include "rk3288-dram-default-timing.dtsi"
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/ {
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aliases {
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mshc0 = &emmc;
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mshc1 = &sdmmc;
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mshc2 = &sdio0;
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mshc3 = &sdio1;
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};
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
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};
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/delete-node/ dmc@ff610000;
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dfi: dfi {
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compatible = "rockchip,rk3288-dfi";
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rockchip,pmu = <&pmu>;
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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dmc: dmc {
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compatible = "rockchip,rk3288-dmc";
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devfreq-events = <&dfi>;
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clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>,
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<&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>,
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<&cru PCLK_DDRUPCTL1>;
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clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0",
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"pclk_phy1", "pclk_upctl1";
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upthreshold = <55>;
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downdifferential = <10>;
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operating-points-v2 = <&dmc_opp_table>;
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vop-dclk-mode = <0>;
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min-cpu-freq = <600000>;
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rockchip,ddr_timing = <&ddr_timing>;
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system-status-freq = <
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/*system status freq(KHz)*/
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SYS_STATUS_NORMAL 396000
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SYS_STATUS_REBOOT 396000
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SYS_STATUS_SUSPEND 192000
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SYS_STATUS_VIDEO_1080P 300000
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SYS_STATUS_VIDEO_4K 396000
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SYS_STATUS_VIDEO_4K_10B 528000
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SYS_STATUS_PERFORMANCE 528000
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SYS_STATUS_BOOST 396000
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SYS_STATUS_DUALVIEW 396000
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SYS_STATUS_ISP 396000
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>;
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auto-min-freq = <396000>;
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auto-freq-en = <0>;
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status = "diasbled";
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};
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dmc_opp_table: opp_table2 {
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compatible = "operating-points-v2";
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opp-192000000 {
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opp-hz = /bits/ 64 <192000000>;
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opp-microvolt = <1100000>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <1100000>;
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};
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opp-396000000 {
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opp-hz = /bits/ 64 <396000000>;
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opp-microvolt = <1100000>;
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};
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opp-528000000 {
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opp-hz = /bits/ 64 <528000000>;
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opp-microvolt = <1150000>;
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};
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};
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reserved-memory {
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ramoops_mem: ramoops@8000000 {
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reg = <0x0 0x8000000 0x0 0xF0000>;
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};
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0 0x0 0x0>;
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};
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
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rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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};
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/delete-node/ timer@ff810000;
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display-subsystem {
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status = "okay";
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ports = <&vopb_out>, <&vopl_out>;
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logo-memory-region = <&drm_logo>;
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route {
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route_hdmi: route-hdmi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_hdmi>;
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};
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route_edp: route-edp {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopl_out_edp>;
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};
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route_dsi0: route-dsi0 {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopl_out_dsi0>;
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};
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route_lvds: route-lvds {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopl_out_lvds>;
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};
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route_rgb: route-rgb {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopl_out_rgb>;
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};
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};
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};
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};
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&dmac_bus_s {
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/* change to non-secure dmac */
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reg = <0x0 0xff600000 0x0 0x4000>;
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};
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&efuse {
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compatible = "rockchip,rk3288-secure-efuse";
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};
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&mpp_srv {
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status = "okay";
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};
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&hevc {
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status = "okay";
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};
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&hevc_mmu {
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status = "okay";
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};
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&iep {
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status = "okay";
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};
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&iep_mmu {
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status = "okay";
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};
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&rga {
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compatible = "rockchip,rga2";
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clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
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clock-names = "aclk_rga", "hclk_rga", "clk_rga";
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status = "okay";
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};
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&rng {
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status = "okay";
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};
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&uart2 {
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status = "disabled";
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};
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&vdpu {
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status = "okay";
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};
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&vepu {
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status = "okay";
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};
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&vpu_mmu {
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status = "okay";
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};
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&video_phy {
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status = "okay";
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};
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