Analog Devices ADF4350/ADF4351 device driver
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Required properties:
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- compatible: Should be one of
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* "adi,adf4350": When using the ADF4350 device
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* "adi,adf4351": When using the ADF4351 device
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- reg: SPI chip select numbert for the device
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- spi-max-frequency: Max SPI frequency to use (< 20000000)
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- clocks: From common clock binding. Clock is phandle to clock for
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ADF435x Reference Clock (CLKIN).
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Optional properties:
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- gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
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pll lock state is tested upon read.
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- adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
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- adi,power-up-frequency: If set in Hz the PLL tunes to
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the desired frequency on probe.
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- adi,reference-div-factor: If set the driver skips dynamic calculation
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and uses this default value instead.
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- adi,reference-doubler-enable: Enables reference doubler.
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- adi,reference-div2-enable: Enables reference divider.
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- adi,phase-detector-polarity-positive-enable: Enables positive phase
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detector polarity. Default = negative.
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- adi,lock-detect-precision-6ns-enable: Enables 6ns lock detect precision.
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Default = 10ns.
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- adi,lock-detect-function-integer-n-enable: Enables lock detect
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for integer-N mode. Default = factional-N mode.
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- adi,charge-pump-current: Charge pump current in mA.
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Default = 2500mA.
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- adi,muxout-select: On chip multiplexer output selection.
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Valid values for the multiplexer output are:
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0: Three-State Output (default)
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1: DVDD
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2: DGND
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3: R-Counter output
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4: N-Divider output
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5: Analog lock detect
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6: Digital lock detect
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- adi,low-spur-mode-enable: Enables low spur mode.
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Default = Low noise mode.
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- adi,cycle-slip-reduction-enable: Enables cycle slip reduction.
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- adi,charge-cancellation-enable: Enabled charge pump
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charge cancellation for integer-N modes.
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- adi,anti-backlash-3ns-enable: Enables 3ns antibacklash pulse width
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for integer-N modes.
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- adi,band-select-clock-mode-high-enable: Enables faster band
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selection logic.
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- adi,12bit-clk-divider: Clock divider value used when
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adi,12bit-clkdiv-mode != 0
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- adi,clk-divider-mode:
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Valid values for the clkdiv mode are:
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0: Clock divider off (default)
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1: Fast lock enable
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2: Phase resync enable
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- adi,aux-output-enable: Enables auxiliary RF output.
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- adi,aux-output-fundamental-enable: Selects fundamental VCO output on
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the auxiliary RF output. Default = Output of RF dividers.
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- adi,mute-till-lock-enable: Enables Mute-Till-Lock-Detect function.
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- adi,output-power: Output power selection.
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Valid values for the power mode are:
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0: -4dBm (default)
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1: -1dBm
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2: +2dBm
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3: +5dBm
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- adi,aux-output-power: Auxiliary output power selection.
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Valid values for the power mode are:
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0: -4dBm (default)
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1: -1dBm
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2: +2dBm
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3: +5dBm
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Example:
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lo_pll0_rx_adf4351: adf4351-rx-lpc@4 {
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compatible = "adi,adf4351";
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reg = <4>;
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spi-max-frequency = <10000000>;
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clocks = <&clk0_ad9523 9>;
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clock-names = "clkin";
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adi,channel-spacing = <10000>;
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adi,power-up-frequency = <2400000000>;
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adi,phase-detector-polarity-positive-enable;
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adi,charge-pump-current = <2500>;
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adi,output-power = <3>;
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adi,mute-till-lock-enable;
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};
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