* Renesas R9A06G032 SYSCTRL
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Required Properties:
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- compatible: Must be:
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- "renesas,r9a06g032-sysctrl"
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- reg: Base address and length of the SYSCTRL IO block.
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- #clock-cells: Must be 1
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- clocks: References to the parent clocks:
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- external 40mhz crystal.
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- external (optional) 32.768khz
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- external (optional) jtag input
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- external (optional) RGMII_REFCLK
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- clock-names: Must be:
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clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
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- #power-domain-cells: Must be 0
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Examples
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--------
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- SYSCTRL node:
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sysctrl: system-controller@4000c000 {
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compatible = "renesas,r9a06g032-sysctrl";
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reg = <0x4000c000 0x1000>;
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#clock-cells = <1>;
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clocks = <&ext_mclk>, <&ext_rtc_clk>,
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<&ext_jtag_clk>, <&ext_rgmii_ref>;
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clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
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#power-domain-cells = <0>;
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};
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- Other nodes can use the clocks provided by SYSCTRL as in:
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#include <dt-bindings/clock/r9a06g032-sysctrl.h>
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uart0: serial@40060000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x40060000 0x400>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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power-domains = <&sysctrl>;
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};
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